Multichannel interface linking a PCM line with a processor

Claim 1

In a communication system including a processor and a data line carrying a multiplicity of PCM channels having respective time slots allocated thereto in a recurrent frame, the combination therewith of a bidirectional interface interposed between said processor and said data line, said interface comprising: input circuitry coupled to said data line for receiving bits of 32 incoming PCM channels therefrom; output circuitry coupled to said data line for transmitting bits of 32 outgoing PCM channels thereto; memory means having sectors individually assignable to incoming and outgoing channels for a temporary storage of bits thereof; access means controlling communication between said memory means and a bus leading to said processor, said access means comprising a single transfer point for bidirectional transmission; and microprogrammed operating means for assigning, with time-division multiplexing, sectors of said memory means to incoming and outgoing channels and controlling the transfer of outgoing bits from said memory means to said output circuitry and of incoming bits from said input circuitry to said memory means in response to instructions from said processor, wherein said microprogrammed operating means comprises a read-only memory containing microprograms conforming to different protocols and manually settable switch means for selecting one of said microprograms to control the transfer of incoming and outgoing bits, and thereby routing same bidirectionally without transfer to a memory of said microprocessor to a predetermined number of bits in each time slot forming a word which is part of an incoming or outgoing message, said operating means including counting means for determining the number of bits during a given time slot in an assigned sector of said memory means, said operating means further including logic means for recognizing signals marking the beginning and the end of a message and reporting same to the processor, said input and output circuitries each comprising an operational logic network controlled by a local time base for registering, during processing of a given channel, a state word relating to such channel and updating said state word in each bit period of a time slot allocated thereto, with transmission of the updated state word to the processor at the end of each time slot.