US4596960A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit
Assignee: Toshiba Corp
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Filing: 1984-03-26
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Granted: 1986-06-24
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Expires: 2004-03-26
Abstract
Abstract A current mirror circuit capable of accurately setting the ratio between input current and output current. The circuit includes a plurality of input terminals and a plurality of output terminals. A plurality of transistor pairs is provided with the first transistor of each pair having its collector connected to an input terminal. In addition, the collector of each first transistor in each pair is coupled to its own base. The bases of the transistors in each pair are coupled together, while the collector of the second transistor in each pair is coupled to an output terminal. The transistors connected to input terminals have their emitters coupled together and grounded through a first resistor. The transistors coupled to output terminals have their emitters coupled together and are grounded through a second resistor. Such a circuit allows ratios between input and output current to be set very accurately.
Inventors
- 👤 Hisakazu Hitomi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:59
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/4508; H03F3/45174; H03F3/34; H03F3/343; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/282; H03K3/2821; H03F2203/00; H03F2203/45; H03F2203/45176
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
306 words
Current mirror apparatus comprising: a plurality of input terminals including at least a first input terminal receiving a first input current and a second input terminal receiving a second input current; a plurality of output terminals including at least a first output terminal providing a first output current and a second output terminal providing a second output current; a plurality of transistor pairs including at least a first pair having first and second transistors and a second pair having third and fourth transistors, the collector of said first transistor being coupled to said first input terminal, the bases of said first and second transistors being coupled together, the emitter of said first transistors being connected to the emitter of said fourth transistor through a first emitter path, the collector of said second transistor being coupled to said first output terminal, the emitter of said second transistor being coupled to the emitter of said third transistor through a second emitter path, the collector of said third transistor being coupled to said second output terminal, the bases of said third and fourth transistors being coupled together, and the collector of said fourth transistor being coupled to said second input terminal; at least a first base current supplying circuit coupling together said first transistor collector and base, and a second base current supplying circuit coupling together said fourth transistor collector and base; means for switching between said first and second input terminals; a first resistor coupled between said first emitter path and ground; and a second resistor coupled between said second emitter path and ground; whereby said first output terminal outputs the first output current when the first input current is supplied to said first input terminal, and said second output terminal outputs the second output current when the second input current is supplied to said second input terminal.
Claim 2
Dependent Claim
306 words
Current mirror apparatus comprising: a plurality of input terminals including at least a first input terminal receiving a first input current and a second input terminal receiving a second input current; a plurality of output terminals including at least a first output terminal providing a first output current and a second output terminal providing a second output current; a plurality of transistor pairs including at least a first pair having first and second transistors and a second pair having third and fourth transistors, the collector of said first transistor being coupled to said first input terminal, the bases of said first and second transistors being coupled together, the emitter of said first transistors being connected to the emitter of said fourth transistor through a first emitter path, the collector of said second transistor being coupled to said first output terminal, the emitter of said second transistor being coupled to the emitter of said third transistor through a second emitter path, the collector of said third transistor being coupled to said second output terminal, the bases of said third and fourth transistors being coupled together, and the collector of said fourth transistor being coupled to said second input terminal; at least a first base current supplying circuit coupling together said first transistor collector and base, and a second base current supplying circuit coupling together said fourth transistor collector and base; means for switching between said first and second input terminals; a first resistor coupled between said first emitter path and ground; and a second resistor coupled between said second emitter path and ground; whereby said first output terminal outputs the first output current when the first input current is supplied to said first input terminal, and said second output terminal outputs the second output current when the second input current is supplied to said second input terminal.
Claim 3
Dependent Claim
15 words
Apparatus according to claim 1 wherein said plurality of transistor pairs includes two transistor pairs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-23 | 1989-12-23 | 1990-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-23 | 1993-12-23 | 1994-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-23 | 1997-12-23 | 1998-06-24 | $7700.00 | Window Closed / Lapsed |