Patent US4596252A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4596252A Expired / Lapsed US ⏱️ 0.0 years remaining

Pacer sense amplifier

Assignee: Medtronic Inc
•
Filing: 1985-05-06
•
Granted: 1986-06-24
•
Expires: 2005-05-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A pacemaker sense amplifier circuit exhibiting a very high common mode rejection ratio for detecting intracardiac electrogram signals is disclosed. The circuit includes a sampling capacitor which is differentially charged by the intracardiac signal. The voltage stored on the sampling capacitor is periodically applied to a high input impedance differential voltage amplifier which is referenced to the battery ground. The signal is smoothed and reconstructed by a bandpass filter, and is applied to a comparator to generate a logic level pulse indicative of the occurrence of a cardiac depolarization.

Inventors

  • 👤 Gary E. Nelson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 15:24
CPC Classifications
A; A61; A61N; A61N1/00; A61N1/18; A61N1/32; A61N1/36; A61N1/362; A61N1/37; A61N1/3702; A61N1/3704; Y; Y10; Y10S; Y10S128/00; Y10S128/902

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 201 words
A pacer sense amplifier circuit for generating a logic level signal in response to sensed intracardiac electrograms (EKG) comprising: a first electrode capable of being coupled to cardiac tissue, for receiving said EKG signals; a second electrode capable of being coupled to cardiac tissue, for receiving said EKG signals; an anti-aliasing filter coupled to said first electrode and said second electrode for defining the frequency domain response of said sense amplifier circuit; a sampling capacity having first and second terminals; a first pair of switches actuated in response to a first clock pulse for coupling said sampling capacitor to said anti-aliasing filter; a buffer amplifier for presenting a high impedance load to said sampling capacitor and presenting a low impedance source to a waveform recovery circuit; a second pair of switches actuated in response to a second clock pulse for coupling said sampling capacitor to said buffer amplifier; a waveform recovery circuit coupled to said buffer amplifier for smoothing the sampled waveform to reconstruct the original EKG waveform; a bandpass/level detector coupled to said waveform recovery circuit for generating a logic level signal whenever said recovered waveform generates sufficient energy within the passband of said detector, indicative of a cardiac depolarization.
Claim 2
Dependent Claim 201 words
A pacer sense amplifier circuit for generating a logic level signal in response to sensed intracardiac electrograms (EKG) comprising: a first electrode capable of being coupled to cardiac tissue, for receiving said EKG signals; a second electrode capable of being coupled to cardiac tissue, for receiving said EKG signals; an anti-aliasing filter coupled to said first electrode and said second electrode for defining the frequency domain response of said sense amplifier circuit; a sampling capacity having first and second terminals; a first pair of switches actuated in response to a first clock pulse for coupling said sampling capacitor to said anti-aliasing filter; a buffer amplifier for presenting a high impedance load to said sampling capacitor and presenting a low impedance source to a waveform recovery circuit; a second pair of switches actuated in response to a second clock pulse for coupling said sampling capacitor to said buffer amplifier; a waveform recovery circuit coupled to said buffer amplifier for smoothing the sampled waveform to reconstruct the original EKG waveform; a bandpass/level detector coupled to said waveform recovery circuit for generating a logic level signal whenever said recovered waveform generates sufficient energy within the passband of said detector, indicative of a cardiac depolarization.

References Cited (Backward Citations)

US4459996A Cited
US4467813A Cited
US4494551A Cited
US4510944A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-06-23 1989-12-23 1990-06-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-06-23 1993-12-23 1994-06-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-06-23 1997-12-23 1998-06-24 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag