Patent US4596069A successfully refreshed from Google Patents.
US4596069A
Expired / Lapsed
US
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Three dimensional processing for monolithic IMPATTs
Assignee: Texas Instruments Inc
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Filing: 1984-07-13
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Granted: 1986-06-24
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Expires: 2004-07-13
Abstract
Abstract The disclosure relates to a monolithic circuit and method of making same which includes the use of two substrates of different semiconductor materials or two substrates of the same semiconductor material wherein the processing steps required for certain parts of the circuit are incompatible with the processing steps required for other parts of the circuit.
Inventors
- 👤 Burhan Bayraktaroglu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:15
CPC Classifications
H; H10; H10P; H10P10/00; H10P10/12; H10P10/128; H10W; H10W20/00; H10W20/20; Y; Y10; Y10S; Y10S148/00; Y10S148/075; Y10S148/135
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
158 words
A method of forming a monolithic semiconductor structure, comprising the steps of: (a) providing a pair of semiconductor wafers, each having an active region on one side thereof, the processing steps to be performed on one of said wafers being incompatible with the processing steps to be performed on the other of said wafers; (b) securing said wafers to a bonding layer disposed therebetween with the active regions thereof facing each other; (c) forming an aperture entirely through one of said wafers extending to said bonding layer; (d) removing the portion of said bonding layer from said aperture; (e) filling said aperture with a heat sink material contacting the other of said wafers; (f) metallizing a predetermined region of the other of said wafers entirely over said heat sink material; (g) removing the other of said wafer except for the portion thereof beneath said metallization; (h) insulating said wafers from each other; and (i) electrically coupling said wafers.
Claim 2
Independent Claim
158 words
A method of forming a monolithic semiconductor structure, comprising the steps of: (a) providing a pair of semiconductor wafers, each having an active region on one side thereof, the processing steps to be performed on one of said wafers being incompatible with the processing steps to be performed on the other of said wafers; (b) securing said wafers to a bonding layer disposed therebetween with the active regions thereof facing each other; (c) forming an aperture entirely through one of said wafers extending to said bonding layer; (d) removing the portion of said bonding layer from said aperture; (e) filling said aperture with a heat sink material contacting the other of said wafers; (f) metallizing a predetermined region of the other of said wafers entirely over said heat sink material; (g) removing the other of said wafer except for the portion thereof beneath said metallization; (h) insulating said wafers from each other; and (i) electrically coupling said wafers.
Claim 3
Dependent Claim
17 words
The method of claim 1 further including, after step (g), removing the remainder of said bonding layer.
Claim 4
Dependent Claim
19 words
The method of claim 1 further including, after step (g), forming a microstrip on said one of said wafers.
Claim 5
Dependent Claim
16 words
The method of claim 2 further including forming a microstrip on said one of said wafers.
Claim 6
Dependent Claim
19 words
The method of claim 1 wherein step (i) comprises forming a conductor over the insulation formed in step (h).
Claim 7
Dependent Claim
19 words
The method of claim 2 wherein step (i) comprises forming a conductor over the insulation formed in step (h).
Claim 8
Dependent Claim
19 words
The method of claim 3 wherein step (i) comprises forming a conductor over the insulation formed in step (h).
Claim 9
Dependent Claim
19 words
The method of claim 4 wherein step (i) comprises forming a conductor over the insulation formed in step (h).
Claim 10
Independent Claim
168 words
A method of forming a monolithic semiconductor structure comprising the steps of: (a) providing first and second semiconductor wafers each having an active region on one surface thereof; (b) securing said wafers to a bonding layer with the active regions facing each other; (c) forming an aperture through a predetermined portion of said first wafer; (d) removing the bonding layer portion exposed in said aperture; (e) filling said aperture with a heat sink material so the said heat sink material contacts the second wafer; (f) removing said second wafer except for said active region; (g) forming an electrically conductive etch stop on the active region of said second wafer only over said heat sink; (h) removing said active layer of said second wafer not beneath said etch stop; (i) removing the remaining bonding layer; (j) forming at least one electrical component on and/or in said first wafer; (k) electrically insulating said first wafer from said second wafer; and (l) electrically coupling said second wafer to said electrical component.
Claim 11
Independent Claim
168 words
A method of forming a monolithic semiconductor structure comprising the steps of: (a) providing first and second semiconductor wafers each having an active region on one surface thereof; (b) securing said wafers to a bonding layer with the active regions facing each other; (c) forming an aperture through a predetermined portion of said first wafer; (d) removing the bonding layer portion exposed in said aperture; (e) filling said aperture with a heat sink material so the said heat sink material contacts the second wafer; (f) removing said second wafer except for said active region; (g) forming an electrically conductive etch stop on the active region of said second wafer only over said heat sink; (h) removing said active layer of said second wafer not beneath said etch stop; (i) removing the remaining bonding layer; (j) forming at least one electrical component on and/or in said first wafer; (k) electrically insulating said first wafer from said second wafer; and (l) electrically coupling said second wafer to said electrical component.
Claim 12
Dependent Claim
17 words
A method as set forth in claim 9 wherein said bonding layer is formed of a polyimide.
Claim 13
Dependent Claim
20 words
A method as set forth in claim 9 wherein said first and second wafers are composed of different semiconductor materials.
Claim 14
Dependent Claim
20 words
A method as set forth in claim 10 wherein said first and second wafers are composed of different semiconductor materials.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-23 | 1989-12-23 | 1990-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-23 | 1993-12-23 | 1994-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-23 | 1997-12-23 | 1998-06-24 | $7700.00 | Window Closed / Lapsed |