FSK data communication system

Claim 1

A system for communicating digital data over a transmission link comprising: transition detector means for detecting high-to-low transitions in the binary logic state of an input digital signal and generating a first transition indicator signal in response thereto, and for detecting low-to-high transitions in the binary logic state of said input digital signal and generating a second transition indicator signal in response thereto; oscillator means for selective generation of an output signal comprising a high-frequency signal at a frequency substantially equal to the baud rate of said input digital signal and a low-frequency signal at a frequency substantially equal to one--half the baud rate of said input digital signal; reset means for resetting said oscillator means to reset said oscillator output signal to a null position in response to each of said first and second transition indicator signals and allowing substantially in-phase switching of said oscillator output signal between said high-frequency and low-frequency signals; switching means for switching said oscillator means between said high-frequency and low-frequency signals in response to said input digital signal, said switching means switching said oscillator means to said high-frequency signal when said input digital signal is at one logic state for producing substantially one cycle of said high-frequency signal corresponding to a bit of said input digital signal at the one logic state, and switching said oscillator means to said low-frequency signal when said input digital signal is at an other logic state for producing substantially one-half cycle of said low-frequency signal corresponding to a bit of said input digital signal at the other logic state to generate a frequency-shift keyed signal to be transmitted over the link; zero-crossing detector means for detecting zero-crossings of said frequency-shift keyed signal received over the link and generating a zero-crossing indicator signal; frequency detector means responsive to said zero-crossing signal for detecting said high-frequency and low-frequency signals of said frequency-shift keyed signal, and generating a frequency indicator signal; and pulse generator means responsive to said zero-crossing indicator signal and said frequency indicator signal for generating an output digital signal corresponding to said input digital signal.

Claim 2

A system for communicating digital data over a transmission link comprising: transition detector means for detecting high-to-low transitions in the binary logic state of an input digital signal and generating a first transition indicator signal in response thereto, and for detecting low-to-high transitions in the binary logic state of said input digital signal and generating a second transition indicator signal in response thereto; oscillator means for selective generation of an output signal comprising a high-frequency signal at a frequency substantially equal to the baud rate of said input digital signal and a low-frequency signal at a frequency substantially equal to one--half the baud rate of said input digital signal; reset means for resetting said oscillator means to reset said oscillator output signal to a null position in response to each of said first and second transition indicator signals and allowing substantially in-phase switching of said oscillator output signal between said high-frequency and low-frequency signals; switching means for switching said oscillator means between said high-frequency and low-frequency signals in response to said input digital signal, said switching means switching said oscillator means to said high-frequency signal when said input digital signal is at one logic state for producing substantially one cycle of said high-frequency signal corresponding to a bit of said input digital signal at the one logic state, and switching said oscillator means to said low-frequency signal when said input digital signal is at an other logic state for producing substantially one-half cycle of said low-frequency signal corresponding to a bit of said input digital signal at the other logic state to generate a frequency-shift keyed signal to be transmitted over the link; zero-crossing detector means for detecting zero-crossings of said frequency-shift keyed signal received over the link and generating a zero-crossing indicator signal; frequency detector means responsive to said zero-crossing signal for detecting said high-frequency and low-frequency signals of said frequency-shift keyed signal, and generating a frequency indicator signal; and pulse generator means responsive to said zero-crossing indicator signal and said frequency indicator signal for generating an output digital signal corresponding to said input digital signal.

Claim 6

A system for communicating digital data over a transmission link, comprising: a first differentiator for differentiating high-to-low transitions of an input digital signal and generating a first transition signal; a second differentiator for differentiating low-to-high transitions of said input digital signal and generating a second transition signal; an oscillator for selective generation of an output signal comprising a high-frequency signal and a low-frequency signal; a reset for resetting said oscillator output signal to a null position in response to each of said first and second transition signals, and providing substantially in-phase switching of said oscillator output signal between said high-frequency and low-frequency signals; a switch for switching said oscillator between said high-frequency and low-frequency signals in response to said input digital signal, said switch switching said oscillator to said high-frequency signal when said input digital signal is at one logic state and switching said oscillator to said low-frequency signal when said input digital signal is at another logic state to generate a frequency-shift keyed signal to be transmitted over the link; squaring means for producing a substantially square wave in response to said frequency-shift keyed signal with transitions substantially corresponding to the zero-crossing of said frequency-shift keyed signal; a first differentiator for differentiating high-to-low transitions of said square wave and generating a first transition signal; a second differentiator for differentiating low-to-high transitions of said square wave and generating a second transition signal; frequency detector means for measuring the time interval between successive signals of said first and second transition signals, and comparing said measured interval to a predetermined time constant to determine if said measured interval corresponds to said high-frequency or low-frequency signal, said frequency detector means generating a frequency indicator signal; and a flip-flop having a data input receiving said frequency indicator signal and a clock input receiving said first and second transition signals for generating an output digital signal corresponding to said input digital signal.

Claim 7

A system for communicating digital data over a transmission link, comprising: a first differentiator for differentiating high-to-low transitions of an input digital signal and generating a first transition signal; a second differentiator for differentiating low-to-high transitions of said input digital signal and generating a second transition signal; an oscillator for selective generation of an output signal comprising a high-frequency signal and a low-frequency signal; a reset for resetting said oscillator output signal to a null position in response to each of said first and second transition signals, and providing substantially in-phase switching of said oscillator output signal between said high-frequency and low-frequency signals; a switch for switching said oscillator between said high-frequency and low-frequency signals in response to said input digital signal, said switch switching said oscillator to said high-frequency signal when said input digital signal is at one logic state and switching said oscillator to said low-frequency signal when said input digital signal is at another logic state to generate a frequency-shift keyed signal to be transmitted over the link; squaring means for producing a substantially square wave in response to said frequency-shift keyed signal with transitions substantially corresponding to the zero-crossing of said frequency-shift keyed signal; a first differentiator for differentiating high-to-low transitions of said square wave and generating a first transition signal; a second differentiator for differentiating low-to-high transitions of said square wave and generating a second transition signal; frequency detector means for measuring the time interval between successive signals of said first and second transition signals, and comparing said measured interval to a predetermined time constant to determine if said measured interval corresponds to said high-frequency or low-frequency signal, said frequency detector means generating a frequency indicator signal; and a flip-flop having a data input receiving said frequency indicator signal and a clock input receiving said first and second transition signals for generating an output digital signal corresponding to said input digital signal.

Claim 8

A system for communicating digital data over a transmission link, comprising: a transition detector for detecting high-to-low transitions in the binary logic state of an input digital signal and generating a first transition indicator signal in response thereto, and for detecting low-to-high transitions in the binary logic state of said input digital signal and generating a second transition indicator signal in response thereto; an oscillator for selective generation of an output signal comprising a high-frequency signal at a frequency substantially equal to the baud rate of said input digital signal and a low frequency signal at a frequency substantially equal to one-half the baud rate of said input digital signal; a reset for resetting said oscillator output signal to a null position in response to each of said first and second transition indicator signals and providing substantially in-phase switching of said oscillator output signal between said high-frequency and low-frequency signals; a switch for switching said oscillator between said high-frequency and low-frequency signals in response to said input digital signal, said switch switching said oscillator to said high-frequency signal when said input digital signal is at one logic state for producing substantially one cycle of said high-frequency signal corresponding to a bit of said input digital signal at the one logic state, and switching said oscillator means to said low-frequency signal when said input digital signal is at an other logic state for producing substantially one-half cycle of said low-frequency signal corresponding to a bit of said input digital signal at the other logic state to generate a frequency-shift keyed signal to be transmitted over the link; a zero-crossing detector for detecting zero-crossings of said frequency-shift keyed signal received over the link and generating a zero-crossing indicator signal; a frequency detector responsive to said zero-crossing signal for detecting said high-frequency and low-frequency signals of said frequency-shift keyed signal, and generating a frequency indicator signal; and a pulse generator responsive to said zero-crossing indicator signal and said frequency indicator signal for generating an output digital signal corresponding to said input digital signal.

Claim 9

A system for communicating digital data over a transmission link, comprising: a transition detector for detecting high-to-low transitions in the binary logic state of an input digital signal and generating a first transition indicator signal in response thereto, and for detecting low-to-high transitions in the binary logic state of said input digital signal and generating a second transition indicator signal in response thereto; an oscillator for selective generation of an output signal comprising a high-frequency signal at a frequency substantially equal to the baud rate of said input digital signal and a low frequency signal at a frequency substantially equal to one-half the baud rate of said input digital signal; a reset for resetting said oscillator output signal to a null position in response to each of said first and second transition indicator signals and providing substantially in-phase switching of said oscillator output signal between said high-frequency and low-frequency signals; a switch for switching said oscillator between said high-frequency and low-frequency signals in response to said input digital signal, said switch switching said oscillator to said high-frequency signal when said input digital signal is at one logic state for producing substantially one cycle of said high-frequency signal corresponding to a bit of said input digital signal at the one logic state, and switching said oscillator means to said low-frequency signal when said input digital signal is at an other logic state for producing substantially one-half cycle of said low-frequency signal corresponding to a bit of said input digital signal at the other logic state to generate a frequency-shift keyed signal to be transmitted over the link; a zero-crossing detector for detecting zero-crossings of said frequency-shift keyed signal received over the link and generating a zero-crossing indicator signal; a frequency detector responsive to said zero-crossing signal for detecting said high-frequency and low-frequency signals of said frequency-shift keyed signal, and generating a frequency indicator signal; and a pulse generator responsive to said zero-crossing indicator signal and said frequency indicator signal for generating an output digital signal corresponding to said input digital signal.

Claim 10

A method for communicating digital data over a transmission link, comprising: detecting high-to-low transitions in the binary logic state of an input digital signal and generating a first transition indicator signal in response thereto; detecting low-to-high transitions in the binary logic state of said input digital signal and generating a second transition indicator signal in response thereto; selectively generating an output signal comprising a high-frequency signal at a frequency substantially equal to the baud rate of said input digital signal and a low-frequency signal at a frequency substantially equal to one-half the baud rate of said input digital signal; resetting said output signal to a null position in response to each of said first and second transition signals and providing substantially in-phase switching of said output signal between said high-frequency and low-frequency signals; switching said output signal between said high-frequency and low-frequency signals in response to said input digital signal, said switching of said output signal to said high-frequency signal occurring when said input digital signal is at one logic state to produce substantially one cycle of said high-frequency signal corresponding to a bit of said input digital signal at the one logic state; and switching said output signal to said low frequency signal occurring when said input digital signal is at an other logic state to provide substantially one-half cycle of said low-frequency signal corresponding to a bit of said input digital signal at the other logic state, thereby generating a frequency shift-keyed signal; detecting zero-crossings of said frequency-shift keyed signal received over the link and generating a zero-crossing indicator signal; detecting said high-frequency and low-frequency signals of said frequency-shift keyed signal from said zero-crossing signal, and generating a frequency indicator signal; and generating an output digital signal corresponding to said input digital signal from said zero-crossing indicator signal and said frequency indicator signal.

Claim 11

A method for communicating digital data over a transmission link, comprising: detecting high-to-low transitions in the binary logic state of an input digital signal and generating a first transition indicator signal in response thereto; detecting low-to-high transitions in the binary logic state of said input digital signal and generating a second transition indicator signal in response thereto; selectively generating an output signal comprising a high-frequency signal at a frequency substantially equal to the baud rate of said input digital signal and a low-frequency signal at a frequency substantially equal to one-half the baud rate of said input digital signal; resetting said output signal to a null position in response to each of said first and second transition signals and providing substantially in-phase switching of said output signal between said high-frequency and low-frequency signals; switching said output signal between said high-frequency and low-frequency signals in response to said input digital signal, said switching of said output signal to said high-frequency signal occurring when said input digital signal is at one logic state to produce substantially one cycle of said high-frequency signal corresponding to a bit of said input digital signal at the one logic state; and switching said output signal to said low frequency signal occurring when said input digital signal is at an other logic state to provide substantially one-half cycle of said low-frequency signal corresponding to a bit of said input digital signal at the other logic state, thereby generating a frequency shift-keyed signal; detecting zero-crossings of said frequency-shift keyed signal received over the link and generating a zero-crossing indicator signal; detecting said high-frequency and low-frequency signals of said frequency-shift keyed signal from said zero-crossing signal, and generating a frequency indicator signal; and generating an output digital signal corresponding to said input digital signal from said zero-crossing indicator signal and said frequency indicator signal.