Patent US4595976A successfully refreshed from Google Patents.
US4595976A
Expired / Lapsed
US
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Inverter control
Assignee: Sundstrand Corp
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Filing: 1984-12-27
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Granted: 1986-06-17
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Expires: 2004-12-27
Abstract
Abstract Prior inverter controls have been developed which are capable of controlling switches in an inverter to produce one of a plurality of polyphase output waveforms. Such controls utilize one or more memories to store a plurality of modulation patterns for controlling the switches. However, such types of inverter controls cannot provide individual phase regulation with the required degree of noise immunity. In order to overcome this problem, an inverter control according to the present invention includes a plurality of memories, one for each phase, each of which is subdivided into a plurality of memory blocks which store a number of bytes, each of which is eight bits in length. Each bit is a zero or one, with a zero representing a first output condition for the respective phase, such as a notch, and a one representing a second output condition, such as a pulse. Memory address decoding logic includes means for accessing a particular memory block in each memory in accordance with a control signal representing the desired waveform to be generated at each phase output. Also included are means for sequentially addressing the bytes within a memory block so that the bytes stored within the block are sequentially provided at an output of the memory. A multiplexer/latch latches a particular bit of each byte so that a control waveform is developed at the output of the latch. The control waveform is utilized to derive operating signals for switches in the respective inverter phase so that the desired waveform is generated. The inverter control of the present invention accomplishes individual phase regulation of the inverter output and is relatively immune to noise which can cause distortion in the output power.
Inventors
- 👤 II Robert C. Parro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:58
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5387; H02M7/53871; H02M7/53873
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
194 words
An inverter control for developing operating signals for switches in an inverter to produce an output in accordance with a control signal, comprising: a memory having a plurality of memory blocks, each memory block storing a series of bytes each comprising a number of bits which may be either a zero or a one, a zero representing a first output condition and a one representing a second output condition; decoding logic coupled to the memory for accessing a particular memory block based upon the control signal; a clock for generating a series of clock pulses; means coupled between the clock and the memory for sequentially addressing the bytes within the accessed memory block as the clock pulses are generated so that such bytes are sequentially provided at an output of the memory; a multiplexer/latch coupled to the memory output and responsive to the control signal for latching a particular bit of each provided byte so that a control waveform is developed at an output thereof; and means coupled to the multiplexer/latch for deriving the operating signals from the control waveform so that an output is produced which assumes the first and second output conditions.
Claim 2
Dependent Claim
194 words
An inverter control for developing operating signals for switches in an inverter to produce an output in accordance with a control signal, comprising: a memory having a plurality of memory blocks, each memory block storing a series of bytes each comprising a number of bits which may be either a zero or a one, a zero representing a first output condition and a one representing a second output condition; decoding logic coupled to the memory for accessing a particular memory block based upon the control signal; a clock for generating a series of clock pulses; means coupled between the clock and the memory for sequentially addressing the bytes within the accessed memory block as the clock pulses are generated so that such bytes are sequentially provided at an output of the memory; a multiplexer/latch coupled to the memory output and responsive to the control signal for latching a particular bit of each provided byte so that a control waveform is developed at an output thereof; and means coupled to the multiplexer/latch for deriving the operating signals from the control waveform so that an output is produced which assumes the first and second output conditions.
Claim 3
Dependent Claim
26 words
The inverter control of claim 1, wherein the sequential addressing means comprises a counter for counting the clock pulses to derive a series of sequential addresses.
Claim 4
Dependent Claim
62 words
The inverter control of claim 1, wherein the inverter produces a polyphase output and wherein the control further includes a memory for each phase, decoding logic coupled to each memory for accessing a memory block therein, each memory being coupled to the sequential addressing means, a multiplexer/latch coupled to each memory output and an operating signal deriving means coupled to each multiplexer/latch.
Claim 5
Dependent Claim
52 words
The inverter control of claim 1, further including means for developing a half cycle signal indicating when a half cycle of the output has been produced and wherein the operating signal deriving means includes an AND gate for combining the half cycle signal and the control waveform to derive the operating signals.
Claim 6
Dependent Claim
47 words
The inverter control of claim 4, wherein the inverter includes two switches and wherein the operating signal deriving means includes a second AND gate for combining the control waveform with an inverted version of the half cycle signal, each AND gate controlling a switch in the inverter.
Claim 7
Dependent Claim
29 words
The inverter control of claim 1, wherein the inverter develops an AC output and wherein each memory block stores the information required to reproduce 180° of th AC output.
Claim 8
Dependent Claim
248 words
An inverter control for developing operating signals for switches in a polyphase inverter to produce one of a plurality of AC outputs in accordance with a control signal, the inverter including a plurality of legs each producing a phase output and including a pair of switches, comprising: a plurality of memories, one for each phase, each memory having a plurality of memory blocks each of which stores a series of bytes, each byte comprising a series of bits each of which may be a zero or a one, a zero representing a first output condition and a one representing a second output condition for the respective phase; a decoding logic circuit coupled to each memory for accessing a memory block in each memory based upon the control signal; a clock for generating a series of clock pulses; means coupled between the clock and the memories for sequentially addressing the bytes within each accessed memory block as the clock pulses are generated so that such bytes are sequentially provided at the outputs of the memories; a multiplexer/latch coupled to each memory output and responsive to the control signal for latching a particular bit of each provided byte so that a plurality of phase control waveforms are developed at an output thereof; and means coupled to each multiplexer/latch for deriving a pair of operating signals for each inverter leg from the phase control waveforms, the pair of operating signals being used to control the pair of switches in the leg.
Claim 9
Dependent Claim
248 words
An inverter control for developing operating signals for switches in a polyphase inverter to produce one of a plurality of AC outputs in accordance with a control signal, the inverter including a plurality of legs each producing a phase output and including a pair of switches, comprising: a plurality of memories, one for each phase, each memory having a plurality of memory blocks each of which stores a series of bytes, each byte comprising a series of bits each of which may be a zero or a one, a zero representing a first output condition and a one representing a second output condition for the respective phase; a decoding logic circuit coupled to each memory for accessing a memory block in each memory based upon the control signal; a clock for generating a series of clock pulses; means coupled between the clock and the memories for sequentially addressing the bytes within each accessed memory block as the clock pulses are generated so that such bytes are sequentially provided at the outputs of the memories; a multiplexer/latch coupled to each memory output and responsive to the control signal for latching a particular bit of each provided byte so that a plurality of phase control waveforms are developed at an output thereof; and means coupled to each multiplexer/latch for deriving a pair of operating signals for each inverter leg from the phase control waveforms, the pair of operating signals being used to control the pair of switches in the leg.
Claim 10
Dependent Claim
26 words
The inverter control of claim 7, wherein the sequential addressing means comprises a counter for counting the clock pulses to derive a series of sequential addresses.
Claim 11
Dependent Claim
64 words
The inverter control of claim 7, further including means for developing a half cycle signal for each phase output indicating when a half cycle of such output has been produced and wherein each operating signal deriving means includes first and second AND gates for combining the half cycle signal and the phase control waveform to in turn control the switches in the respective leg.
Claim 12
Dependent Claim
21 words
The inverter control of claim 7, wherein each memory block stores the information required to reproduce 180° of each phase output.
Claim 13
Dependent Claim
35 words
The inverter control of claim 7, wherein each decoding logic circuit includes means for accessing a different memory block in accordance with a new control signal only during a particular point in the phase output.
Claim 14
Dependent Claim
138 words
An inverter control for developing operating signals for switches in an inverter so that the inverter produces one of a plurality of pulse width modulated (PWM) outputs in accordance with a control signal, comprising: a memory having a plurality of memory blocks, each memory block storing a series of zeroes and ones, a zero representing a first output condition and a one representing a second output condition, the series of zeroes and ones representing 180° of a particular PWM output; means for developing a clock signal; means coupled to the memory for repetitively accessing in sequential fashion the series of zeroes and ones in accordance with the clock signal to produce a control waveform; and means coupled to the accessing means for deriving the operating signals from the control waveform so that the particular PWM output is produced.
Claim 15
Dependent Claim
138 words
An inverter control for developing operating signals for switches in an inverter so that the inverter produces one of a plurality of pulse width modulated (PWM) outputs in accordance with a control signal, comprising: a memory having a plurality of memory blocks, each memory block storing a series of zeroes and ones, a zero representing a first output condition and a one representing a second output condition, the series of zeroes and ones representing 180° of a particular PWM output; means for developing a clock signal; means coupled to the memory for repetitively accessing in sequential fashion the series of zeroes and ones in accordance with the clock signal to produce a control waveform; and means coupled to the accessing means for deriving the operating signals from the control waveform so that the particular PWM output is produced.
Claim 16
Dependent Claim
21 words
The inverter control of claim 12, wherein the accessing means comprises a counter having an input coupled to the clock signal.
Claim 17
Dependent Claim
52 words
The inverter control of claim 12, further including means for developing a half cycle signal indicating when a half cycle of the output has been produced and wherein the operating signal deriving means includes an AND gate for combining the half cycle signal and the control waveform to derive the operating signals.
Claim 18
Dependent Claim
47 words
The inverter control of claim 14, wherein the inverter includes two switches and wherein the operating signal deriving means includes a second AND gate for combining the control waveform with an inverted version of the half cycle signal, each AND gate controlling a switch in the inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-16 | 1989-12-16 | 1990-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-16 | 1993-12-16 | 1994-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-16 | 1997-12-16 | 1998-06-17 | $7700.00 | Window Closed / Lapsed |