US4593373A
Expired / Lapsed
US
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Method and apparatus for producing n-bit outputs from an m-bit microcomputer
Assignee: Sharp Corp
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Filing: 1983-08-09
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Granted: 1986-06-03
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Expires: 2003-08-09
Abstract
Abstract A one-chip microcomputer system includes an arithmetic and logic unit (ALU) for processing data in an m-bit order. A random access memory is provided, which has a plurality of memory areas each of which is made of m bits. A plurality of memory areas are aligned in the horizontal direction so that the total memory bits in the horizontal direction exceeds n bits. When the row address data and the column address data are applied to an addressing circuit, a desired data of m bits is read out from the random access memory and is applied to the ALU. If only the row address data is applied to the addressing circuit, all data included in a selected row is applied to an output control circuit. The output control circuit latches n bits, whereby n-bit data is developed from the output control circuit to another electronic apparatus.
Inventors
- 👤 Akihiro Kiuchi
- 👤 Shinichi Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:53
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/04
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
212 words
A microcomputer system comprising: arithmetic and logic unit means for processing m-bit data; random access memory means for storing the m bit data having a plurality of memory cells that are aligned in a matrix fashion, the number of said memory cells that are aligned in a first direction being greater than or equal to a bit number n; output control means for latching n-bit data and receiving the n-bit data, where n is greater than m; addressing means for selecting desired memory cells in said random access memory means, said addressing means including first address means for selecting desired memory cells along said first direction, and second address means for selecting desired memory cells along a second direction which is different from said first direction in said matrix fashion; control means includable in said arithmetic and logic unit for selectively enabling said addressing means, whereby m-bit data is read out from the random access memory means and is applied to said arithmetic and logic unit means when both of said first and second address means are enabled, and n-bit data is read out from the random access memory means and is applied to said output control means when said first address means is enabled and said second address means is disabled.
Claim 2
Dependent Claim
212 words
A microcomputer system comprising: arithmetic and logic unit means for processing m-bit data; random access memory means for storing the m bit data having a plurality of memory cells that are aligned in a matrix fashion, the number of said memory cells that are aligned in a first direction being greater than or equal to a bit number n; output control means for latching n-bit data and receiving the n-bit data, where n is greater than m; addressing means for selecting desired memory cells in said random access memory means, said addressing means including first address means for selecting desired memory cells along said first direction, and second address means for selecting desired memory cells along a second direction which is different from said first direction in said matrix fashion; control means includable in said arithmetic and logic unit for selectively enabling said addressing means, whereby m-bit data is read out from the random access memory means and is applied to said arithmetic and logic unit means when both of said first and second address means are enabled, and n-bit data is read out from the random access memory means and is applied to said output control means when said first address means is enabled and said second address means is disabled.
Claim 3
Dependent Claim
247 words
A microcomputer system comprising: arithmetic and logic unit means for processing m-bit data; output control means for latching n-bit data and receiving tne n-bit data, where n is greater than or equal to m; random access memory means having at least one memory area in the horizontal direction and a plurality of memory areas in the vertical direction, thereby providing memory areas aligned in a matrix fashion, each of said memory areas having m bits in the horizontal direction, and the total memory bits in said horizontal direction of said random access memory means being greater than or equal to the bit number n; addressing means for selecting desired memory areas in said random access memory means, said addressing means including; a row decoder for selecting desired memory areas aligned in said horizontal direction; a column decoder for selecting desired memory areas aligned in said vertical direction; and control means includable in said arithmetic and logic unit for selectively enabling said addressing means, whereby m-bit data is read out from said random access memory means and is applied to said arithmetic and logic unit means when both the row decoder and column decoder are supplied with address data, and data of which bit number is greater than or equal to n is read out from said random access memory means and is applied to said output control means when said row decoder is supplied with address data and address data is not applied to said column decoder.
Claim 4
Dependent Claim
247 words
A microcomputer system comprising: arithmetic and logic unit means for processing m-bit data; output control means for latching n-bit data and receiving tne n-bit data, where n is greater than or equal to m; random access memory means having at least one memory area in the horizontal direction and a plurality of memory areas in the vertical direction, thereby providing memory areas aligned in a matrix fashion, each of said memory areas having m bits in the horizontal direction, and the total memory bits in said horizontal direction of said random access memory means being greater than or equal to the bit number n; addressing means for selecting desired memory areas in said random access memory means, said addressing means including; a row decoder for selecting desired memory areas aligned in said horizontal direction; a column decoder for selecting desired memory areas aligned in said vertical direction; and control means includable in said arithmetic and logic unit for selectively enabling said addressing means, whereby m-bit data is read out from said random access memory means and is applied to said arithmetic and logic unit means when both the row decoder and column decoder are supplied with address data, and data of which bit number is greater than or equal to n is read out from said random access memory means and is applied to said output control means when said row decoder is supplied with address data and address data is not applied to said column decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-02 | 1989-12-02 | 1990-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-02 | 1993-12-02 | 1994-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-02 | 1997-12-02 | 1998-06-03 | $7700.00 | Window Closed / Lapsed |