Array processor for digital computers

Claim 2

In a digital computer wherein the element of a plurality of arrays of digital numbers are stored at known addresses in its memory, such computer being actuated by a sequence of instruction words to process selected ones of such arrays, each one of the instruction words thereof including an operation code, an operand address code and an array dimension code, a processor for combining the elements of selected ones of such arrays, such processor comprising: a. an array store having a plurality of addresses; b. array store addressing and actuating means, responsive to the operand address code and to the array dimension code in a first one of the instruction words, for transferring each element of a first array of digital numbers from its known address in the memory to a known address in the array store and for storing the operation code and at least a portion of the array dimension code of the first one of the instruction words at different known addresses in the array store; c. array element selecting means, responsive to the portion of the array dimension code in the array store and reSponsive to the operand address code and to the array dimension code in a second one of the instruction words, for sequentially retrieving the elements of the first array of digital numbers in a first order from the array store and for sequentially retrieving the elements of a second array of digital numbers in a second order from the memory; and, d. combining means, responsive to the operation code stored in the array store and to the operation code in the second instruction word, for combining the elements of the first and second array of digital numbers as such numbers are retrieved.

Claim 3

In a digital computer for processing matrices of digital numbers, the elements of each one of such matrices being stored at known addresses in the computer''s memory, such computer being responsive to an operand address code in each one of a sequence of instruction words to select the address of the first element in each one of the matrices to be processed, each one of the instruction words further including an operation code and a matrix dimension code to define the number of rows, columns and elements in each one of the matrices, a processor to multiply selected elements in a selected pair of such matrices, such processor comprising: a. means, responsive to the operand address code and to the matrix dimension code in a first instruction word, for transferring the elements of a first one of the matrices from the computer''s memory to successive addresses in a matrix store; b. means, responsive to the operation code and to the matrix dimension code in the first instruction word, for storing such operation code and matrix dimension code; c. means, responsive to the operand address code in a second instruction word, for retrieving the first element in a second one of the matrices from the computer''s memory; d. arithmetic means for multiplying selected elements in the first and the second one of such matrices to derive partial results, each one of such results being a part of an element in a resulting matrix; and e. matrix element selecting means, responsive to the matrix dimension code in the first and the second instruction word for successively impressing the elements in the first column of the first one of the matrices in the matrix store and the first element in the second one of the matrices of the arithmetic means and then the elements in each successive column of the first one of the matrices with a successive one of the elements in the second one of the matrices.

Claim 4

In a digital computer for processing matrices of digital numbers, the elements of each one of such matrices being stored at known addresses in the computer''s memory, such computer being responsive to an operand address code in each one of a sequence of instruction words to select the address of the first element in each one of the matrices to be processed, each one of the instruction words further including an operation code and a matrix dimension code to define the number of rows, columns and elements in each one of the matrices, a processor to multiply selected elements in a selected pair of such matrices, such processor comprising: a. means, responsive to the operand address code and to the matrix dimension code in a first instruction word, for transferring the elements of a first one of the matrices from the computer''s memory to successive addresses in a matrix store; b. means, responsive to the operation code and to the matrix dimension code in the first instruction word, for storing such operation code and matrix dimension code; c. means, responsive to the operand address code in a second instruction word, for retrieving the first element in a second one of the matrices from the computer''s memory; d. arithmetic means for multiplying selected elements in the first and the second one of such matrices to derive partial results, each one of such results being a part of an element in a resulting matrix; and e. matrix element selecting means, responsive to the matrix dimension code in the first and the second instruction word for successively impressing the elements in the first column of the first one of the matrices in the matrix store and the first element in the second one of the matrices of the arithmetic means and then the elements in each successive column of the first one of the matrices with a successive one of the elements in the second one of the matrices.

Claim 5

A processor as in claim 2 having additionally, answer storage means, responsive to the matrix dimension code in the first one of the instruction words, for storing each partial result out of the arithmetic means at a known address in such storage means.

Claim 6

A processor as in claim 3 having additionally, adder means in the arithmetic means for adding the partial result at each known address in the answer storage means to predetermined ones of the partial results out of the multiplying means.

Claim 7

A processor as in claim 4 having additionally: a. means, responsive to the matrix dimension code in the first and the second instruction words, for determining when the partial results in the answer storage means correspond to elements in the resulting matrix; b. means for then transferring each one of the elements in the answer storage means to a known address in the computer''s memory; and, c. means for repeating the multiplication and adding of elements in the first and the second matrix and transfer of elements in the resulting matrix until all of the elements of such matrix are transferred to known addresses in the computer''memory.

Claim 8

In a processor for a digital computer adapted to combine, in response to three successive instruction words retrieved from a memory along with the elements of a first and a second matrix to be combined to form a third matrix, each one of such words including an operation code, an operand address code and a matrix contrOl code to control the operation of the processor and the digital computer, the improvement comprising: a. address counter means for the third matrix, responsive to the matrix control code in the first instruction word, for receiving the operand address code in such word; b. first matrix control and storage means, responsive to the matrix control code in the second instruction word, for inhibiting operation of the third matrix address counter means and for storing the elements of the first matrix, the operation code in the second instruction word and a first coded signal representative of a first selected dimension of the first matrix; and c. processor control means, responsive to the operation code, the operand address code and the matrix control code in the third instruction word and to the codes stored in the first matrix control and storage means, for enabling the third matrix address counter means for combining the elements of the first and the second matrix to form, successively, subgroups of the elements of the third matrix and to store each successively formed subgroup in said memory.

Claim 9

In a processor for a digital computer adapted to combine, in response to three successive instruction words retrieved from a memory along with the elements of a first and a second matrix to be combined to form a third matrix, each one of such words including an operation code, an operand address code and a matrix contrOl code to control the operation of the processor and the digital computer, the improvement comprising: a. address counter means for the third matrix, responsive to the matrix control code in the first instruction word, for receiving the operand address code in such word; b. first matrix control and storage means, responsive to the matrix control code in the second instruction word, for inhibiting operation of the third matrix address counter means and for storing the elements of the first matrix, the operation code in the second instruction word and a first coded signal representative of a first selected dimension of the first matrix; and c. processor control means, responsive to the operation code, the operand address code and the matrix control code in the third instruction word and to the codes stored in the first matrix control and storage means, for enabling the third matrix address counter means for combining the elements of the first and the second matrix to form, successively, subgroups of the elements of the third matrix and to store each successively formed subgroup in said memory.