US4593300A
Expired / Lapsed
US
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Folded logic gate
Assignee: University of Minnesota Twin Cities
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Filing: 1984-10-31
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Granted: 1986-06-03
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Expires: 2004-10-31
Abstract
Abstract An FET logic gate structure includes two semiconductor layers separated by an insulator. An enhancement mode switching FET is formed in the top semiconductor layer, and a load element is formed in the bottom semiconductor layer. The insulator layer separates and capacitively couples the switching element and the load element so that the switching element acts as a gate for the load element and the load element acts as a second gate of the switching element. An input is connected to the gate of the switching element. The drain of the switching element, the source of the load element, and the output of the folded logic gate are connected together. The logic gate structure exhibits very low power consumption in stable states, high speed and large output voltage swings.
Inventors
- 👤 Michael Shur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:35
CPC Classifications
H; H10; H10D; H10D88/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
130 words
A logic gate comprising: a FET switching element having a first gate, a drain, a source and a channel of a first conductivity type; a load element having a drain, a source and a channel of the first conductivity type, the source of the load element being located generally under the source of the FET switching element; means for electrically connecting the source of the load element to the drain of the FET switching element; and a low conductivity layer positioned between the FET switching element and the load element for separating and capacitively coupling the FET switching element and the load element so that the switching element acts as a gate for the load element and the load element acts as a second gate of the FET switching element.
Claim 2
Dependent Claim
130 words
A logic gate comprising: a FET switching element having a first gate, a drain, a source and a channel of a first conductivity type; a load element having a drain, a source and a channel of the first conductivity type, the source of the load element being located generally under the source of the FET switching element; means for electrically connecting the source of the load element to the drain of the FET switching element; and a low conductivity layer positioned between the FET switching element and the load element for separating and capacitively coupling the FET switching element and the load element so that the switching element acts as a gate for the load element and the load element acts as a second gate of the FET switching element.
Claim 3
Dependent Claim
41 words
The logic gate of claim 1 and further comprising: an input terminal connected to the gate of the FET switching element; and an output terminal connected to the drain of the FET switching element and the source of the load element.
Claim 4
Dependent Claim
23 words
The logic gate of claim 2 and further comprising: means for electrically connecting the drain of the load element to a bias voltage.
Claim 5
Dependent Claim
82 words
The logic gate of claim 3 wherein the channel of the load element has a carrier concentration which for values of drain voltage V d of the FET switching element near zero causes one end of the channel to be totally depleted, which for values of V d near the bias voltage cause an opposite end of the channel to be totally depleted, and which for intermediate values of V d cause the channel to be partially depleted along its entire length.
Claim 6
Dependent Claim
16 words
The logic gate of claim 1 wherein the FET switching element is an enhancement mode FET.
Claim 7
Dependent Claim
15 words
The logic gate of claim 1 wherein the FET switching element is a normally-on FET.
Claim 8
Dependent Claim
144 words
A logic gate comprising: a first semiconductor layer; a second semiconductor layer positioned below the first semiconductor layer; a low conductivity layer positioned between the first and second semiconductor layers; a FET formed in the first semiconductor layer, the FET having a first gate, a source, a drain, and a channel of a first conductivity type between the source and drain; and a load element formed in the second semiconductor layer, the load element having a source, a drain and a channel of the first conductivity type between the source and drain, the load element capacitively coupled to the FET so that the channel of the FET acts as a gate for the load element and the load element acts as a second gate for the FET; and means for electrically connecting the source of the load element to the drain of the FET.
Claim 9
Dependent Claim
144 words
A logic gate comprising: a first semiconductor layer; a second semiconductor layer positioned below the first semiconductor layer; a low conductivity layer positioned between the first and second semiconductor layers; a FET formed in the first semiconductor layer, the FET having a first gate, a source, a drain, and a channel of a first conductivity type between the source and drain; and a load element formed in the second semiconductor layer, the load element having a source, a drain and a channel of the first conductivity type between the source and drain, the load element capacitively coupled to the FET so that the channel of the FET acts as a gate for the load element and the load element acts as a second gate for the FET; and means for electrically connecting the source of the load element to the drain of the FET.
Claim 10
Dependent Claim
30 words
The logic gate of claim 7 and further comprising: an input terminal connected to the gate of the FET; and an output terminal connected to the drain of the FET.
Claim 11
Dependent Claim
23 words
The logic gate of claim 8 and further comprising: means for electrically connecting the drain of the load element to a bias voltage.
Claim 12
Dependent Claim
21 words
The logic gate of claim 7 wherein the source of the load element is located generally under the source of FET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-02 | 1989-12-02 | 1990-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-02 | 1993-12-02 | 1994-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-02 | 1997-12-02 | 1998-06-03 | $7700.00 | Window Closed / Lapsed |