Low power liquid crystal display driver circuit

Claim 1

A display driver circuit comprising: first means for providing at least a timing signal; second means for providing at least first and second voltage levels; input circuit means for receiving data to be displayed; segment output circuit means connected to said input circuit means for driving of display segments and including for each display segment an associated first switching means having an output alternating between the first and second voltage levels in response to corresponding data to be displayed and the timing signal to provide an output signal at an output node and thereby to the display segment associated with the first switching means; display timing circuit means for providing time interval signal outputs connected to said display segments, said display timing circuit means includes second switching means that provide said time interval signal outputs by alternately connecting the first voltage level and second voltage level in response to the timing signal to the time interval signal outputs, wherein the first and second switching means each include first and second capacitors connected together in series at a node for receipt of the timing signal and having a first end and a second end, and first and second field effect transistors connected together in series between the first voltage level and the second voltage level having a common output node for connection to the display segments, the first end connected to the gate of the first field effect transistor and the second end connected to the gate of the second field effect transistor.