Patent US4593270A successfully refreshed from Google Patents.
US4593270A
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Successive approximation analog to digital converter
Assignee: Texas Instruments Tucson Corp
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Filing: 1984-06-19
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Granted: 1986-06-03
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Expires: 2004-06-19
Abstract
Abstract An analog-to-digital converter is used in conjunction with a digital to analog converter and a comparison network to provide a group of digital signals that, when applied to a digital-to-analog converter, produce an output signal approximating an applied input signal. The analog-to-digital converter includes a clock circuit, a series of bistable multivibrator circuits, a master latch circuit, a plurality of slave latch circuits, and associated logic circuits. The bistable multivibrators are arranged to produce a sequence of activation signals in response to operation of the clock circuit. The activation signals serve to place slave latches circuits sequentially in a positive logic status temporarily, each slave latch output terminal being associated with a binary signal of decreasing significance in approximating the applied input signal. The output signal of the digital-to-analog converter is compared with the applied input signal. A signal resulting from the comparison of these signals is applied through the master latch circuit to the activated slave latch circuit and this comparison signal determines whether a positive or negative logic signal is latched at the output terminal of the slave latch circuit. The multivibrator circuits then activate the next slave latch circuit in sequence until the last slave latch circuit is activated. The analog-to-digital converter is implemented in current mode (steering mode) logic and compatible components to permit the circuit to be fabricated on a single chip.
Inventors
- 👤 Robert White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:49
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/14; H03M1/16; H03M1/164
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
122 words
A successive approximation register for receiving an input signal, comprising: a plurality of data latch circuits; a plurality of flip-flop circuits, each of said flip-flop circuits coupled to a one of said data latch circuits, said plurality of flip-flop circuits adapted to activate said coupled data latch circuits in a sequential order, each of said activated data latch circuits providing a first signal to be applied to output terminals, said activated data latch circuit storing said first or a second signal in response to said input signal; and a master data latch circuit coupled to said plurality of data latch circuits, said master data latch circuit applying an output signal to said plurality of data latch circuits determined by said input signal.
Claim 2
Dependent Claim
122 words
A successive approximation register for receiving an input signal, comprising: a plurality of data latch circuits; a plurality of flip-flop circuits, each of said flip-flop circuits coupled to a one of said data latch circuits, said plurality of flip-flop circuits adapted to activate said coupled data latch circuits in a sequential order, each of said activated data latch circuits providing a first signal to be applied to output terminals, said activated data latch circuit storing said first or a second signal in response to said input signal; and a master data latch circuit coupled to said plurality of data latch circuits, said master data latch circuit applying an output signal to said plurality of data latch circuits determined by said input signal.
Claim 3
Dependent Claim
38 words
The successive approximation register of claim 1 further including a clock circuit, said clock circuit activated in response to an initiate signal, said clock circuit causing said flip-flop circuits to activate said data latch circuits in sequential order.
Claim 4
Dependent Claim
31 words
The successive approximation register of claim 1 or 2 wherein said circuits are implemented with current mode logic components and compatible components, said converter being fabricated on a single semiconductor chip.
Claim 5
Dependent Claim
31 words
The successive approximation register of claim 1 wherein said circuits include a voltage sensing means for compensating for a voltage drop in conducting leads coupling said circuits with a power supply.
Claim 6
Dependent Claim
26 words
The successive approximation register of claim 2 wherein said clock circuit includes a differential amplifier for developing a constant clock period over a range of temperatures.
Claim 7
Dependent Claim
34 words
The successive approximation register of claims 1 or 2 wherein input signals of said differential circuits are coupled in a single ended mode and compared against a one of a plurality of reference voltages.
Claim 8
Dependent Claim
145 words
For use in conjunction with a digital-to-analog converter and a comparator circuit, apparatus for providing successive approximation analog-to-digital conversion responsive to a condition signal and an initial signal comprising: a clock circuit for providing a series of pulses in response to said initial signal; a plurality of slave data latch circuits enabled in a predetermined sequence in response to said clock pulses, each of said enabled slave data latch circuits applying a preselected logic signal to an output terminal when said slave data latch circuit is enabled; and a master latch circuit coupled to said plurality of slave data latch circuits for receiving said condition signal and said preselected logic signal, said master latch causing a logic signal to be stored in said enabled slave data latch circuit determined by said condition signal upon activation of a next slave data latch in said predtermined sequence.
Claim 9
Dependent Claim
145 words
For use in conjunction with a digital-to-analog converter and a comparator circuit, apparatus for providing successive approximation analog-to-digital conversion responsive to a condition signal and an initial signal comprising: a clock circuit for providing a series of pulses in response to said initial signal; a plurality of slave data latch circuits enabled in a predetermined sequence in response to said clock pulses, each of said enabled slave data latch circuits applying a preselected logic signal to an output terminal when said slave data latch circuit is enabled; and a master latch circuit coupled to said plurality of slave data latch circuits for receiving said condition signal and said preselected logic signal, said master latch causing a logic signal to be stored in said enabled slave data latch circuit determined by said condition signal upon activation of a next slave data latch in said predtermined sequence.
Claim 10
Dependent Claim
47 words
The apparatus for providing an analog-to-digital conversion of claim 7 further including a plurality of flip-flop circuits coupled to said clock circuit for sequentially activating said plurality of data latch circuits, wherein activation of all of said flip-flop circuits causes a signal to terminate said clock pulses.
Claim 11
Dependent Claim
23 words
The apparatus for providing an analog-to-digital conversion of claim 8 wherein said apparatus is a circuit element implemented in current mode logic technology.
Claim 12
Dependent Claim
30 words
The apparatus for providing an analog-to-digital conversion of claim 7 wherein said circuits include a sense line means for minimizing conductor voltage drop between said elements and a power supply.
Claim 13
Dependent Claim
133 words
A circuit element for storing a multiplicity of logic signal states in response to a multiplicity of condition signals comprising: a clock circuit for providing a sequence of pulses; a multiplicity of flip-flop circuits coupled to said clock circuit, said clock pulses activating said multiplicity of flip-flop circuits in a predetermined sequence; a multiplicity of slave data latch circuits, each slave data latch circuit associated with a one of said flip-flop circuits and activated when said associated flip-flop is activated, said slave data latch circuits initially applying a predetermined logic signal when activated; and a master latch circuit coupled to said slave latch circuits for receiving said multiplicity of condition signals, wherein said slave data latch stores a logic state related to said condition signals when a test sequential flip-flop circuit is activated.
Claim 14
Dependent Claim
133 words
A circuit element for storing a multiplicity of logic signal states in response to a multiplicity of condition signals comprising: a clock circuit for providing a sequence of pulses; a multiplicity of flip-flop circuits coupled to said clock circuit, said clock pulses activating said multiplicity of flip-flop circuits in a predetermined sequence; a multiplicity of slave data latch circuits, each slave data latch circuit associated with a one of said flip-flop circuits and activated when said associated flip-flop is activated, said slave data latch circuits initially applying a predetermined logic signal when activated; and a master latch circuit coupled to said slave latch circuits for receiving said multiplicity of condition signals, wherein said slave data latch stores a logic state related to said condition signals when a test sequential flip-flop circuit is activated.
Claim 15
Dependent Claim
17 words
The circuit element of claim 11 wherein said circuit element is implemented in current mode logic technology.
Claim 16
Dependent Claim
30 words
The circuit element of claim 12 wherein said flip-flop circuits and said data latch circuits have a sense line means for minimizing effects of a potential voltage drop along conductors.
Claim 17
Dependent Claim
22 words
The circuit element of claim 12 wherein differential amplifiers in said data latch and flip-flop circuits are configured in a single-input mode.
Claim 18
Dependent Claim
32 words
The circuit element of claim 12 wherein said clock circuit includes differential switch pairs; and, means for developing a constant current ratio in said differential switch pairs over a range of temperatures.
Claim 19
Dependent Claim
18 words
The circuit element of claim 12 wherein activation of a last flip-flop circuit halts said sequence of pulses.
References Cited (Backward Citations)
US4454500A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-02 | 1989-12-02 | 1990-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-02 | 1993-12-02 | 1994-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-02 | 1997-12-02 | 1998-06-03 | $7700.00 | Window Closed / Lapsed |