US4592076A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizing signal recovery circuit for radiotelephones
Assignee: Japan Radio Co Ltd
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Filing: 1983-07-29
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Granted: 1986-05-27
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Expires: 2003-07-29
Abstract
Abstract An improved circuit for synchronizing signal recovery particularly suitable for mobile radiotelephone operation is disclosed. The initializing circuit of the phase-locked loop in the data receiver is inhibited for a predetermined duration upon triggering of a "window mode" by either of a rising or falling pulse-edge in a sequence of "ones" or "zeros" in the received data. The window mode masks the invalid transitions in such sequences and prevents retriggering by such transitions.
Inventors
- 👤 Mahmoud A. S. El-Banna
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:48
CPC Classifications
H; H04; H04M; H04M1/00; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0079; H04L7/0083; H04L7/0087
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
122 words
An improved synchronizing signal recovery circuit in a receiver for data signals having a predetermined word rate, a predetermined bit rate, and a predetermined synchronizing character rate, comprising: generating means for acquiring a stable clock from said data signals at said bit rate; initializing means responsive to said data signals for initializing said generating means; first inhibiting means for inhibiting said initializing means from reinitializing said generating means for a predetermined duration upon being triggered by one of rising and falling pulse-edges in said data signals; indicating means for indicating recognition of a synchronizing character; and second inhibiting means responsive to said first inhibiting means and to said indicating means for inhibiting said generating means from recommencing acquisition of said stable clock.
Claim 2
Dependent Claim
122 words
An improved synchronizing signal recovery circuit in a receiver for data signals having a predetermined word rate, a predetermined bit rate, and a predetermined synchronizing character rate, comprising: generating means for acquiring a stable clock from said data signals at said bit rate; initializing means responsive to said data signals for initializing said generating means; first inhibiting means for inhibiting said initializing means from reinitializing said generating means for a predetermined duration upon being triggered by one of rising and falling pulse-edges in said data signals; indicating means for indicating recognition of a synchronizing character; and second inhibiting means responsive to said first inhibiting means and to said indicating means for inhibiting said generating means from recommencing acquisition of said stable clock.
Claim 3
Dependent Claim
19 words
The improved synchronizing signal recovery circuit as defined in claim 1 said generating means being a digital phase-locked loop.
Claim 4
Dependent Claim
19 words
The improved synchronizing signal recovery circuit as defined in claim 1, said generating means being a digital phase-locked loop.
Claim 5
Dependent Claim
34 words
The improved synchronizing signal recovery circuit as defined in claim 1, said second inhibiting means being a monostable circuit for generating a pair of opposite polarity pulses for a preselected duration upon being triggered.
Claim 6
Dependent Claim
30 words
The improved synchronizing signal recovery circuit as defined in claim 1, said generating means being a digital phase-locked loop having a phase detector input responsive to said second inhibiting means.
Claim 7
Dependent Claim
63 words
The improved synchronizing signal recovery circuit as defined in claim 5, said first inhibiting means comprising first and second monostable circuits, each inhibiting the other once triggered, one responsive to rising and the other to falling pulse-edges, and both having their outputs OR-ed to generate an inhibiting signal for said predetermined duration upon either of them being triggered by one of said pulse-edges.
Claim 8
Dependent Claim
34 words
The improved synchronizing signal recovery circuit as defined in claim 5, said second inhibiting means being a monostable circuit for generating a pair of opposite polarity pulses for a preselected duration upon being triggered.
Claim 9
Dependent Claim
63 words
The improved synchronizing signal recovery circuit as defined in claim 1, said first inhibiting means comprising first and second monostable circuits, each inhibiting the other once triggered, one responsive to rising and the other to falling pulse-edges, and both having their outputs OR-ed to generate an inhibiting signal for said predetermined duration upon either of them being triggered by one of said pulse-edges.
Claim 10
Dependent Claim
34 words
The improved synchronizing signal recovery circuit as defined in claim 8, said second inhibiting means being a monostable circuit for generating a pair of opposite polarity pulses for a preselected duration upon being triggered.
Claim 11
Dependent Claim
139 words
An improved synchronizing signal recovery circuit in a receiver for data signals having a predetermined word rate, a predetermined bit rate, and a predetermined synchronizing character rate, comprising: generating means for acquiring a stable clock from said data signals at said bit rate; initializing means responsive to said data signals for initializing said generating means; and first inhibiting means for inhibiting said initializing means from reinitializing said generating means for a predetermined duration upon being triggered by one of rising and falling pulse-edges in said data signals; said first inhibiting means comprising first and second monostable circuits, each inhibiting the other once triggered, one responsive to rising and the other to falling pulse-edges, and both having their outputs OR-ed to generate an inhibiting signal for said predetermined duration upon either of them being triggered by one of said pulse-edges.
Claim 12
Dependent Claim
139 words
An improved synchronizing signal recovery circuit in a receiver for data signals having a predetermined word rate, a predetermined bit rate, and a predetermined synchronizing character rate, comprising: generating means for acquiring a stable clock from said data signals at said bit rate; initializing means responsive to said data signals for initializing said generating means; and first inhibiting means for inhibiting said initializing means from reinitializing said generating means for a predetermined duration upon being triggered by one of rising and falling pulse-edges in said data signals; said first inhibiting means comprising first and second monostable circuits, each inhibiting the other once triggered, one responsive to rising and the other to falling pulse-edges, and both having their outputs OR-ed to generate an inhibiting signal for said predetermined duration upon either of them being triggered by one of said pulse-edges.
References Cited (Backward Citations)
US3613015A
Cited
US4464771A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-26 | 1989-11-25 | 1990-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-26 | 1993-11-25 | 1994-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-26 | 1997-11-25 | 1998-05-27 | $7700.00 | Window Closed / Lapsed |