US3613015A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary digital data detection system
Assignee: Unisys Corp
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Filing: 1969-11-12
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Granted: 1971-10-12
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Expires: 1989-11-12
Abstract
Abstract An improved strobe pulse generator system for self-clocking data systems wherein a resettable strobe pulse generator is prevented from resetting during a data pulse. The input data is applied to an AND gate the output of which is coupled to the strobe pulse generator to first set the strobe pulse and then after a delay to reset the strobe pulse generator. The reset coupling is through an inhibit gate which also receives the input data through an inverter. The inhibit gate and the inverter operate to prevent resetting the strobe pulse generator during the receipt of a data pulse.
Inventors
- 👤 Harry W Lewis
- 👤 Edmund J Mcbride
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:12
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
179 words
In a digital data system which includes intermixed data and clock pulses arranged in a serial pulse train, means for separating the clock pulses from the data pulses comprising a two-input AND gate for receiving on one input said serial pulse train, a strobe pulse generator, coupling means coupling the output of said AND gate to said pulse generator, said coupling means comprising a first signal path responsive to a clock pulse output from said AND gate to inaugurate the generation of a strobe pulse and a second signal path responsive to said clock pulse after a delay to terminate the generation of the strobe pulse; means for applying said strobe pulse to the second input of said AND gate to inhibit operation thereof during the presence of said strobe pulse, whereby clock pulses May be derived from the output of said AND gate, the second signal path of said coupling means further including an inhibit means responsive to the input serial pulse train for inhibiting the termination of said strobe pulse during the receipt of a data pulse.
Claim 2
Dependent Claim
179 words
In a digital data system which includes intermixed data and clock pulses arranged in a serial pulse train, means for separating the clock pulses from the data pulses comprising a two-input AND gate for receiving on one input said serial pulse train, a strobe pulse generator, coupling means coupling the output of said AND gate to said pulse generator, said coupling means comprising a first signal path responsive to a clock pulse output from said AND gate to inaugurate the generation of a strobe pulse and a second signal path responsive to said clock pulse after a delay to terminate the generation of the strobe pulse; means for applying said strobe pulse to the second input of said AND gate to inhibit operation thereof during the presence of said strobe pulse, whereby clock pulses May be derived from the output of said AND gate, the second signal path of said coupling means further including an inhibit means responsive to the input serial pulse train for inhibiting the termination of said strobe pulse during the receipt of a data pulse.
Claim 3
Dependent Claim
52 words
A system as set forth in claim 1 wherein said pulse generator is a flip-flop and wherein the first signal path of said coupling means is connected to the set input of said flip-flop and the second signal path of said coupling means is coupled to the reset input of said flip-flop.
Claim 4
Dependent Claim
36 words
A system as set forth in claim 2 wherein the second signal path includes a triggerable delay device and an AND gate coupling the output of said delay device to the reset terminal of said flip-flop.
Claim 5
Dependent Claim
38 words
A system as set forth in claim 3 wherein an inverter couples the input signal train to the AND gate of said second signal path so as to inhibit said AND gate during receipt of the data pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-11 | 1975-04-12 | 1975-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-11 | 1979-04-12 | 1979-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-11 | 1983-04-12 | 1983-10-12 | $7700.00 | Window Closed / Lapsed |