Patent US4590552A successfully refreshed from Google Patents.
US4590552A
Expired / Lapsed
US
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Security bit for designating the security status of information stored in a nonvolatile memory
Assignee: Texas Instruments Inc
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Filing: 1982-06-30
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Granted: 1986-05-20
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Expires: 2002-06-30
Abstract
Abstract A digital processing device implemented on a single semiconductor substrate includes an nonvolatile memory for the storage of data and instructions that define operations on the data. The memory is connected to an inhibit logic interface which is in turn connected to an information bus. The information bus is connected to a central processor that performs the operations on data. An external interface is also connected to the information bus to provide information on the information bus to external devices. At least one security bit is provided for designating security status of information stored in the memory. Address logic is connected to the information bus to determine when information is being accessed from the memory. Security control circuitry is also provided and is connected to the central processing unit, the address logic, to determine when an instruction is being fetched by the central processing unit and if the instruction is being fetched from the memory. The security control circuitry is connected to the inhibit logic interface to inhibit the information bus interface to the memory during selected operations in the central processing unit.
Inventors
- 👤 Karl M. Guttag
- 👤 Steve Nussrallah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:51
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
318 words
A digital processing device implemented on a single semiconductor substrate comprising: a nonvolatile memory means for storing data and instructions that define data processing operations; an information transfer means for transferring data and instructions; a first inhibit logic means connected between said nonvolatile memory means and said information transfer means for selectively inhibiting transfer of data and instructions from said nonvolatile memory means to said information transfer means; a central processing unit connected to said information transfer means for performing data processing operations defined by instructions received from said information transfer means; at least one security bit register connected to said central processing unit, each security bit register having a state indicating a protected or nonprotected status of a corresponding portion of said nonvolatile memory means; an external interface means connected to said information transfer means for transfer of data and instructions between said digital processing device and at least one external device; an external interface inhibit logic means connected to said external interface means for selectively inhibiting transfer of data and instructions by said external interface means; an instruction acquisition means connected to said information transfer means for indicating when data or instructions within said nonvolatile memory means are being accessed; and a security control means connected to said information transfer means, said first inhibit logic means, said external interface inhibit logic means, said at least one security bit register and said central processing unit for determining when an instruction is being fetched and further connected to said instruction acquisition logic to indicate when a protected status portion of said nonvolatile memory means is being accessed and for selectively causing said first inhibit logic means and said external interface inhibit logic means to inhibit data and instruction transfer upon performance of selected operations by said central processing unit, thereby preventing unauthorized access to data and instructions stored in said protected, status portion of said nonvolatile memory means.
Claim 2
Dependent Claim
318 words
A digital processing device implemented on a single semiconductor substrate comprising: a nonvolatile memory means for storing data and instructions that define data processing operations; an information transfer means for transferring data and instructions; a first inhibit logic means connected between said nonvolatile memory means and said information transfer means for selectively inhibiting transfer of data and instructions from said nonvolatile memory means to said information transfer means; a central processing unit connected to said information transfer means for performing data processing operations defined by instructions received from said information transfer means; at least one security bit register connected to said central processing unit, each security bit register having a state indicating a protected or nonprotected status of a corresponding portion of said nonvolatile memory means; an external interface means connected to said information transfer means for transfer of data and instructions between said digital processing device and at least one external device; an external interface inhibit logic means connected to said external interface means for selectively inhibiting transfer of data and instructions by said external interface means; an instruction acquisition means connected to said information transfer means for indicating when data or instructions within said nonvolatile memory means are being accessed; and a security control means connected to said information transfer means, said first inhibit logic means, said external interface inhibit logic means, said at least one security bit register and said central processing unit for determining when an instruction is being fetched and further connected to said instruction acquisition logic to indicate when a protected status portion of said nonvolatile memory means is being accessed and for selectively causing said first inhibit logic means and said external interface inhibit logic means to inhibit data and instruction transfer upon performance of selected operations by said central processing unit, thereby preventing unauthorized access to data and instructions stored in said protected, status portion of said nonvolatile memory means.
Claim 3
Dependent Claim
36 words
The digital processing system according to claim 1, wherein said security control means inhibits said first inhibit logic means when an instruction obtained from said external interface means is being executed in said central processing means.
Claim 4
Dependent Claim
308 words
A digital processing device implemented on a single semiconductor substrate comprising: a nonvolatile memory means for storing data and instructions that define data processing operations; an information transfer means for transferring data and instructions; an inhibt logic means connected to said nonvolatile memory means and said information transfer means for selectively inhibiting transfer to data and instructions from said nonvolatile memory means to said information transfer means; a central processing unit connected to said information transfer means for performing data processing operations defined by instructions received from said information transfer means; at least one security bit register connected to said central processing unit, each security bit register having a state indicating a protected or nonprotected status of a corresponding portion of said nonvolatile memory means; an external interface means connected to said lnformation transfer means for transfer of data and instructions between said digital processing device and at least one external device; an instruction acquisition means connected to said information transfer means for indicating when data or instructions within said nonvolatile memory means are being accessed; and a security control means connected to said information transfer means, said inhibit logic means, said at least one security bit register and said central processing unit for determining when an instruction is being fetched and further connected to said instruction acquisition logic to indicate when a protected status portion of said nonvolatile memory means is being accessed and for causing said inhibit logic means to inhibit data and instruction transfer from said nonvolatile memory means to said information transfer means upon performance of a memory access operation to said protected status portion of said nonvolatile memory means by said central processing unit in accordance with an instruction from said external interface means, thereby preventing unauthorized access to data and instructions stored in said protected status portion of said nonvolatile memory means.
Claim 5
Dependent Claim
308 words
A digital processing device implemented on a single semiconductor substrate comprising: a nonvolatile memory means for storing data and instructions that define data processing operations; an information transfer means for transferring data and instructions; an inhibt logic means connected to said nonvolatile memory means and said information transfer means for selectively inhibiting transfer to data and instructions from said nonvolatile memory means to said information transfer means; a central processing unit connected to said information transfer means for performing data processing operations defined by instructions received from said information transfer means; at least one security bit register connected to said central processing unit, each security bit register having a state indicating a protected or nonprotected status of a corresponding portion of said nonvolatile memory means; an external interface means connected to said lnformation transfer means for transfer of data and instructions between said digital processing device and at least one external device; an instruction acquisition means connected to said information transfer means for indicating when data or instructions within said nonvolatile memory means are being accessed; and a security control means connected to said information transfer means, said inhibit logic means, said at least one security bit register and said central processing unit for determining when an instruction is being fetched and further connected to said instruction acquisition logic to indicate when a protected status portion of said nonvolatile memory means is being accessed and for causing said inhibit logic means to inhibit data and instruction transfer from said nonvolatile memory means to said information transfer means upon performance of a memory access operation to said protected status portion of said nonvolatile memory means by said central processing unit in accordance with an instruction from said external interface means, thereby preventing unauthorized access to data and instructions stored in said protected status portion of said nonvolatile memory means.
Claim 6
Dependent Claim
144 words
The digital processing device according to claim 3, further comprising: a temporary read/write memory means for temporary storage of data and instructions; a second inhibit logic means connected between said temporary read/write memory means and said information transfer means for selectively inhibiting transfer of data and instructions between said temporary read/write means and said information transfer means; and said security control means is further connected to said second inhibit logic means and further includes means for detecting when data or instructions within said temporary read/write memory means is being accessed and for selectively causing said second inhibit logic means to inhibit such a data and instruction transfer upon performance of a memory access operation by said central processing unit in accordance with an instruction form said external interface means, thereby preventing unauthorized access to data and instructions stored in said temporary read/write memory means.
Claim 7
Dependent Claim
48 words
The digital processing device according to claim 4, wherein each of said at least one security bit register is located adjacent to said corresponding portion of said nonvolatile memory means to prevent deprogramming of the security bit register without deprogramming said corresponding portion of said nonvolatile memory means.
Claim 8
Dependent Claim
23 words
The digital processing system according to claim 5, wherein said security bit register includes means to protect the security bit register from alteration.
Claim 9
Dependent Claim
31 words
The digital processing device according to claim 4, wherein a portion of said temporary read/write memory is accessible by said information transfer means and not inhibited by said security control means.
Claim 10
Dependent Claim
18 words
The digital processing device implemented according to claim 7, wherein said temporary memory includes a random access memory.
Claim 11
Dependent Claim
38 words
A digital processing device according to claim 7, wherein said security control means prohibits the transfer of information from a protected area in the nonvalatile memory or the temporary memory to an unprotected area in the temporary memory.
Claim 12
Dependent Claim
274 words
A digital processing device implemented on a single seniconductor substrate comprising: a nonvolatile memory means for storing data and instructions that define data processing operations; an information transfer means for transferring data and instructions; a central processing unit connected to said information transfer means for performing data processing operations defined by instructions received from said information transfer means; at least one seucrity bit register connected to said central processing unit, each security bit register having a state indicating a protected or nonprotected status of a corresponding portion of said nonvolatile memory means; an external interface means connected to said information transfer means for transfer of data and instructions between said digital processing device and at least one external device; an inhibit logic means connected to said external interface means for selectively inhibiting transfer of data and instruction by said external interface means; an instruction acquisition means connected to said information transfer means for indicating when data or instructions within said nonvolatile memory means are being accessed; and a security control means connected to said information transfer means, said inhibit logic means, said at least one security bit register and said central processing unit for determining when data or instructions from said external interface means is being accessed and for selectively causing said inhibit logic means to inhibit data and instruction transfer by said external interface means upon performance of an external interface means access operation by said central processing unit in accordance with an instruction from a protected status portion of said nonvolatile memory means, thereby preventing unauthorized access to data and instructions stored in said protected status portion of said nonvolatile memory means.
Claim 13
Dependent Claim
274 words
A digital processing device implemented on a single seniconductor substrate comprising: a nonvolatile memory means for storing data and instructions that define data processing operations; an information transfer means for transferring data and instructions; a central processing unit connected to said information transfer means for performing data processing operations defined by instructions received from said information transfer means; at least one seucrity bit register connected to said central processing unit, each security bit register having a state indicating a protected or nonprotected status of a corresponding portion of said nonvolatile memory means; an external interface means connected to said information transfer means for transfer of data and instructions between said digital processing device and at least one external device; an inhibit logic means connected to said external interface means for selectively inhibiting transfer of data and instruction by said external interface means; an instruction acquisition means connected to said information transfer means for indicating when data or instructions within said nonvolatile memory means are being accessed; and a security control means connected to said information transfer means, said inhibit logic means, said at least one security bit register and said central processing unit for determining when data or instructions from said external interface means is being accessed and for selectively causing said inhibit logic means to inhibit data and instruction transfer by said external interface means upon performance of an external interface means access operation by said central processing unit in accordance with an instruction from a protected status portion of said nonvolatile memory means, thereby preventing unauthorized access to data and instructions stored in said protected status portion of said nonvolatile memory means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-19 | 1989-11-18 | 1990-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-19 | 1993-11-18 | 1994-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-19 | 1997-11-18 | 1998-05-20 | $7700.00 | Window Closed / Lapsed |