Device for generating a frequency modulated signal

Claim 3

A device according to claim 1, wherein the error correction means comprises a delay circuit that, controlled by the said error signal (S e ), applies a variable delay to said output signal.

Claim 4

A device according to claim 2, wherein the error correction means further comprises, at the output of the delay circuit and connected in series; an amplitude/phase detector supplied at a first input by the delayed output signal; an amplifier; and a frequency-controlled oscillator circuit having an output which is applied to a second input of the amplitude/phase detector.

Claim 5

A device according to claim 2, wherein said delay circuit is a delay line with multiple outputs selected by a commutation circuit.

Claim 6

A device according to claim 2 wherein said delay circuit is a continuous variation device controlled by the error signal (S e ) through the intermediary of a digital/analogue converter.

Claim 7

A device according to claim 5, wherein said delay circuit comprises a comparator with a variable threshold, supplied by the output signal, delayed or not, filtered by a filtering circuit.

Claim 8

A device according to claim 5, wherein said delay circuit comprises a variable delay monostable multivibrator.

Claim 9

A device according to claim 1, wherein said error correction means comprises in series: an amplitude/phase detector supplied on a first input by the signal s(t) delievered by the digital generator; an adder circuit receiving on a positive input an output signal from said amplitude/phase detector and on a negative input the error signal (Se) through the intermediary of a digital/analog converter; and an oscillator circuit frequency controlled by an output signal from said adder circuit, through the intermediary of an amplifier, an output of the oscillator circuit being applied to a second input of the amplitude/phase detector.

Claim 10

A device according to claim 3, wherein said oscillator circuit comprises: a first oscillator frequency controlled by the signal s(t) delivered by the digital generator; a second oscillator providing a steady frequency signal; a mixer receiving at a first input a variable frequency signal delivered by said first oscillator and at a second input said steady frequency signal delivered by said second oscillator; and, a frequency divider circuit that receives an output signal from said mixer and provides an output signal to said second input of the amplitude/phase detector.

Claim 11

A device according to claim 3, wherein said oscillator circuit receives an anticipation signal (S a ) representing a predetermined theoretical frequency modiculation law to be generated, corresponding to said predetermined law.

Claim 12

A device according to claim 1, wherein said digital generator comprises: a programmable divider generating a signal s(t) of which each period of rank number k is an integer multiple N k higher than 1, k varying from 0 to n, of the period T of the clock signal, and is as close as possible to a corresponding period of the theoretical signal (S t ); memory means supplying (n+1) integers (N o , . . . , N k , . . . , N n ) successively to the programmable divider and the said error signal (S e ); addressing means for controlling the memory means; and control means for actuating said device and its interruption at the end of read-out of the contents of the memory means, and the reinitialization of the programmable divider, the memory means and the addressing means being both controlled by a signal sampled at the output of the said programmable divider.

Claim 13

A device according to claim 1, wherein the programmable divider is a decounter of which the contents undergo, at each clock cycle, a decrementation of one unit from the value N k -1, the integer N k being supplied by memory means at the beginning of each counting cycle, until the value 0 indicating the end of the counting cycle of rank k and corresponding to the emission by the decounter of a pulse that coincides with the Nth and last clock cycle of the kth counting cycle, this pulse provoking the charge in the decounter of the value N k+1 -1, the integers N k with k ranging between 0 and n, being successively supplied by memory means addressed by the addressing means.

Claim 14

A device according to claim 11, wherein the programmable divider includes a counter of which the contents undergo at each clock cycle an incrementation of one unit from the value N M+1 -N k until the value N M indicating the end of the counting cycle of rank k and corresponding to the emission by the counter of one impulse that coincides with the Nth and last clock cycle of the kth counting cycle, this pulse provoking the charge in the counter of the value N M +1-N k+1 , the integers N k being successively supplied by memory means and N M being the maximum given value that can be displayed by the counter.

Claim 15

A device according to claim 11, wherein the memory means comprises: a memory circuit containing n+1 variations existing between two successive division rank numbers (N k .1, N k ), and n+1 errors (ε o , . . . , ε k , . . . , ε n ) at n+1 respective addresses controlled by the addressing means and successively delivering from each address, of rank k varying from 0 to n, the error (ε k ) that forms the error signal (S e ) to said error correction means, and the variation (ΔNk) to said programmable divider; and a calculating circuit that is initialized at an initial value N' o , positive integer, by said control means and which, controlled by said sampled signal successively calculates the n+1 rank (No=N' o +ΔNo, Ni,=No+ΔN1, . . . , N k =N k-1 +ΔN k , . . . , N n =N n-1 +ΔN n ) of the divisions carried out by the programmable divider, each rank-number k (N k ) being equal to the total of the preceding rank-number of division (N o ) of rank 0 equal to the sum of the initial value N' o and of the variation value (ΔN o ) of rank 0, and said memory circuit delivering at the same time as the last variation (Δ n ) an end-of-sequence signal (S f ) to the control means.

Claim 16

A device according to claim 14, wherein successive ranks of division (N o , . . . , N k , . . . , N n ) differ at most by one unit, and wherein the memory circuit comprises an addressable read-only memory, emitting each variation in the form of two binary elements (e, b), and an AND gate combining the said two binary elements (a, b) in order to form the end-of sequence signal (S f ), and wherein the calculating circuit comprises a counter/decounter circuit initialized at value N' o by said control means and supplied by said two binary elements (a, b) each combined with the signal sampled at the output of the programmable divider in an AND gate.

Claim 17

A device according to claim 11, wherein said control means include a bistable R/S flip-flop, supplied on its inputs (S, R), respectively, by the external control signal (S d ) and the end-of-sequence signal (S f ) and delivers an initialization signal (S i ) to the programmable divider, the memory means and the addressing means.

Claim 18

A device according to claim 11, wherein said digital generator further comprises, downstream from the programmable divider, a bistable flip-flop delivering a signal of which the rising fronts and the falling front respectively correspond to the instants wherein the phase of the signal s(t) delivered by the digital generator is an even or uneven multiple respectively of π.