US4589096A
Expired / Lapsed
US
⏱️ 0.0 years remaining
IIL semiconductor memory including arrangement for preventing information loss during read-out
Assignee: Hitachi Ltd
•
Filing: 1983-03-17
•
Granted: 1986-05-13
•
Expires: 2003-03-17
Abstract
Abstract A semiconductor memory having memory cells in each of which emitter terminals and first collector terminals of two IIL unit circuits are cross-connected to each other, injector regions and a common emitter region of the two IIL unit circuits are respectively connected to upper and lower word lines, and second collectors of the IIL unit circuits are respectively connected to a pair of bit lines that are respectively connected through load elements to a power source higher in voltage than the lower word line. This serves to hold the bit line potential higher than the lower word line potential to ensure that transistors formed by the second collectors, the emitters and the bases are inversely operated to prevent information loss during a read operation.
Inventors
- 👤 Kenji Kaneko
- 👤 Takahiro Okabe
- 👤 Minoru Nagata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:27
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; G11C11/411; G11C11/4113; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
182 words
A semiconductor memory comprising: memory cells each including first and second IIL unit circuits, each of which includes an emitter region of a first conductivity type, a base region of a second conductivity type formed in said emitter region, first and second collector regions of the first conductivity type formed in said base region, and an injector region of the second conductivity type formed in said emitter region and separated from said base region, and in which said first collector regions and said base regions are cross-connected to each other; an upper word line connected to said injector regions of said memory cells; a lower word line connected to said emitter regions of said memory cells; and pairs of bit lines, the bit lines of each pair being respectively connected to said second collector regions of said first and second IIL unit circuits and being respectively connected through load elements to a power source of a predetermined voltage so that said second collector regions operate as collectors and said emitter regions operate as emitters in a reading operation of said memory cells.
Claim 2
Dependent Claim
182 words
A semiconductor memory comprising: memory cells each including first and second IIL unit circuits, each of which includes an emitter region of a first conductivity type, a base region of a second conductivity type formed in said emitter region, first and second collector regions of the first conductivity type formed in said base region, and an injector region of the second conductivity type formed in said emitter region and separated from said base region, and in which said first collector regions and said base regions are cross-connected to each other; an upper word line connected to said injector regions of said memory cells; a lower word line connected to said emitter regions of said memory cells; and pairs of bit lines, the bit lines of each pair being respectively connected to said second collector regions of said first and second IIL unit circuits and being respectively connected through load elements to a power source of a predetermined voltage so that said second collector regions operate as collectors and said emitter regions operate as emitters in a reading operation of said memory cells.
Claim 3
Dependent Claim
15 words
A semiconductor memory according to claim 1, wherein said each load element is a resistor.
Claim 4
Dependent Claim
165 words
A semiconductor memory comprising: memory cells each including first and second IIL unit circuits, each of which includes an emitter region of a first conductivity type, a base region of a second conductivity type formed in said emitter region, first and second collector regions of the first conductivity type formed in said base region, and an injector region of the second conductivity type formed in said emitter region and separated from said base region, and in which said first collector regions and said base regions are cross-connected to each other, pairs of bit lines, the bit lines of each pair being respectively connected to said second collector regions of said first and second IIL unit circuits, an upper and a lower word line, said injector regions being connected to said upper word line and said emitter regions being connected to said lower word line, and means coupled to said bit lines for holding said bit lines at a higher potential than said lower word line.
Claim 5
Dependent Claim
165 words
A semiconductor memory comprising: memory cells each including first and second IIL unit circuits, each of which includes an emitter region of a first conductivity type, a base region of a second conductivity type formed in said emitter region, first and second collector regions of the first conductivity type formed in said base region, and an injector region of the second conductivity type formed in said emitter region and separated from said base region, and in which said first collector regions and said base regions are cross-connected to each other, pairs of bit lines, the bit lines of each pair being respectively connected to said second collector regions of said first and second IIL unit circuits, an upper and a lower word line, said injector regions being connected to said upper word line and said emitter regions being connected to said lower word line, and means coupled to said bit lines for holding said bit lines at a higher potential than said lower word line.
Claim 6
Dependent Claim
196 words
A semiconductor memory comprising: memory cells each including first and second IIL unit circuits, each of which includes an emitter region of a first conducitivity type, a base region of a second conductivity type formed in said emitter region, first and second collector regions of the first conductivity type formed in said base region, and an injector region of the second conductivity type formed in said emitter region and separated from said base region, and in which said first collector regions and said base regions are cross-connected to each other, pairs of bit lines, the bit lines of each pair being respectively connected to said second collector regions of said first and second IIL unit circuits, an upper and a lower word line, said injector regions being connected to said upper word line and said emitter regions being connected to said lower word line, and means coupled to said bit lines for holding said bit lines at a higher potential than said lower word line to inversely operate inverse transistors each of which is formed of said second collector region, said base region and said emitter region to prevent information loss from said memory during read-out.
Claim 7
Dependent Claim
196 words
A semiconductor memory comprising: memory cells each including first and second IIL unit circuits, each of which includes an emitter region of a first conducitivity type, a base region of a second conductivity type formed in said emitter region, first and second collector regions of the first conductivity type formed in said base region, and an injector region of the second conductivity type formed in said emitter region and separated from said base region, and in which said first collector regions and said base regions are cross-connected to each other, pairs of bit lines, the bit lines of each pair being respectively connected to said second collector regions of said first and second IIL unit circuits, an upper and a lower word line, said injector regions being connected to said upper word line and said emitter regions being connected to said lower word line, and means coupled to said bit lines for holding said bit lines at a higher potential than said lower word line to inversely operate inverse transistors each of which is formed of said second collector region, said base region and said emitter region to prevent information loss from said memory during read-out.
Claim 8
Dependent Claim
179 words
A semiconductor memory comprising: memory cells each including first and second IIL unit circuits, each of which includes an emitter region of n-type conductivity, a base region of p-type conductivity formed in said emitter region, first and second collector regions of n-type conductivity formed in said base region, and an injector region of p-type conductivity formed in said emitter region and separated from said base region, and in which said first collector regions and said base regions are cross-connected to each other; an upper word line connected to said injector regions of said memory cells; a lower word line connected to said emitter regions of said memory cells; and pairs of bit lines, the bit lines of each pair being respectivley connected to said second collector regions of said first and second IIL unit circuits and being respectively connected through load elements to a power source of a predetermined voltage which is higher than the voltage of said lower word line so that currents are absorbed from said bit lines into said second collector regions in a reading operation.
Claim 9
Dependent Claim
179 words
A semiconductor memory comprising: memory cells each including first and second IIL unit circuits, each of which includes an emitter region of n-type conductivity, a base region of p-type conductivity formed in said emitter region, first and second collector regions of n-type conductivity formed in said base region, and an injector region of p-type conductivity formed in said emitter region and separated from said base region, and in which said first collector regions and said base regions are cross-connected to each other; an upper word line connected to said injector regions of said memory cells; a lower word line connected to said emitter regions of said memory cells; and pairs of bit lines, the bit lines of each pair being respectivley connected to said second collector regions of said first and second IIL unit circuits and being respectively connected through load elements to a power source of a predetermined voltage which is higher than the voltage of said lower word line so that currents are absorbed from said bit lines into said second collector regions in a reading operation.
References Cited (Backward Citations)
US4322820A
Cited
US4374431A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-12 | 1989-11-11 | 1990-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-12 | 1993-11-11 | 1994-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-12 | 1997-11-11 | 1998-05-13 | $7700.00 | Window Closed / Lapsed |