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US4588904A Expired / Lapsed US ⏱️ 0.0 years remaining

High efficiency bias circuit for high frequency inductively loaded power switching transistor

Assignee: Nokia Bell Labs
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Filing: 1983-09-16
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Granted: 1986-05-13
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Expires: 2003-09-16
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Abstract

Abstract A turn off circuit for an inductivity loaded power switching transistor utilizes a transistor current path in the base circuit and two series connected diode junctions in the emitter circuit to reverse bias the base-emitter junction of the power switching transistor without the need for an active reverse bias voltage source.

Inventors

  • 👤 Miroslav Glogolja

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 14:43
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0416; H03K17/04166

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 184 words
A power switching circuit comprising: a transistor switch including a collector, an emitter and a base; a second transistor having a first conductivity type and connected to couple a turn-on bias voltage to the base of the transistor switch; a third transistor having a second conductivity type opposite the first conductivity type and including a collector emitter path connected to couple the base of the transistor switch to ground potential and operative as a low impedance current path to bias the transistor switch nonconducting; logic means for applying a common bias signal to base electrodes at the second and third transistors so that the second and third transistors are always in opposite conductivity modes; first and second diodes connected in series coupling the emitter of the transistor switch to ground, and providing sufficient voltage drop so that a voltage drop across the first and second diodes exceeds a voltage drop across the collector emitter path of the third transistor when it is conducting; and an anti-saturation diode coupling the base electrode of the second and third transistors to the collector of the transistor switch.
Claim 2
Dependent Claim 184 words
A power switching circuit comprising: a transistor switch including a collector, an emitter and a base; a second transistor having a first conductivity type and connected to couple a turn-on bias voltage to the base of the transistor switch; a third transistor having a second conductivity type opposite the first conductivity type and including a collector emitter path connected to couple the base of the transistor switch to ground potential and operative as a low impedance current path to bias the transistor switch nonconducting; logic means for applying a common bias signal to base electrodes at the second and third transistors so that the second and third transistors are always in opposite conductivity modes; first and second diodes connected in series coupling the emitter of the transistor switch to ground, and providing sufficient voltage drop so that a voltage drop across the first and second diodes exceeds a voltage drop across the collector emitter path of the third transistor when it is conducting; and an anti-saturation diode coupling the base electrode of the second and third transistors to the collector of the transistor switch.
Claim 3
Dependent Claim 195 words
A power switching circuit comprising: a transistor switch including a collector, an emitter and a base; means for controlling a conductivity state of the transistor switch including; second and third transistors of opposite conductivity type to one another and having their emitter electrodes joined in common to the base of the transistor switch; drive control means coupled to control a conductivity state of the second and third transistors in opposite modes of conductivity including a binary logic circuit coupled to apply bilevel signals in common to base electrodes of the second and third transistors, the third transistor coupling a bias voltage to bias the transistor switch conductive and the second transistor coupling a ground reference to bias the transistor switch nonconductive; at least first and second diodes coupling the emitter of the transistor switch to the ground reference and operative for maintaining the emitter at the transistor switch at a slightly higher voltage than a voltage drop across a collector emitter path at the second transistor when it is conducting; and a feedback path including an anti-saturation diode coupling a base electrode at the second and third transistors to the collector of the transistor switch.
Claim 4
Dependent Claim 195 words
A power switching circuit comprising: a transistor switch including a collector, an emitter and a base; means for controlling a conductivity state of the transistor switch including; second and third transistors of opposite conductivity type to one another and having their emitter electrodes joined in common to the base of the transistor switch; drive control means coupled to control a conductivity state of the second and third transistors in opposite modes of conductivity including a binary logic circuit coupled to apply bilevel signals in common to base electrodes of the second and third transistors, the third transistor coupling a bias voltage to bias the transistor switch conductive and the second transistor coupling a ground reference to bias the transistor switch nonconductive; at least first and second diodes coupling the emitter of the transistor switch to the ground reference and operative for maintaining the emitter at the transistor switch at a slightly higher voltage than a voltage drop across a collector emitter path at the second transistor when it is conducting; and a feedback path including an anti-saturation diode coupling a base electrode at the second and third transistors to the collector of the transistor switch.
Claim 5
Dependent Claim 28 words
A power switch as defined in claim 2 wherein recovery time of the first and second diodes is slow relative to a switching speed at the transistor switch.

References Cited (Backward Citations)

US3073969A Cited
US3235746A Cited
US3243510A Cited
US4239989A Cited
US4221979A Cited
US4266149A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-05-12 1989-11-11 1990-05-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-05-12 1993-11-11 1994-05-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-05-12 1997-11-11 1998-05-13 $7700.00 Window Closed / Lapsed

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