US4587655A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fail-safe system for vehicular computer
Assignee: Honda Motor Co Ltd
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Filing: 1983-10-12
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Granted: 1986-05-06
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Expires: 2003-10-12
Abstract
Abstract A fail-safe computer system for vehicle control, the system comprising a CPU having at least two computer status information outputs and an interruption request input. The system further comprises a detecting logic circuit having the inputs thereof coupled to the status information outputs and having the output thereof coupled to the interruption request input, wherein upon detection of a HALT signal at any of the status outputs by the logic circuit, the logic circuit applies an output to the interruption request input whereby the computer system is reset to a predetermined state thereof.
Inventors
- 👤 Yoshikazu Hirao
- 👤 Shigeo Umesaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:56
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0796; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
120 words
A fail-safe computer system for vehicle control, said system comprising: (a) a CPU means having at least two CPU status information outputs and an interruption request input; (b) a detecting logic circuit means having the inputs thereof coupled to said status information outputs and having the output thereof coupled to said interruption request input, wherein upon detection of a HALT signal at any of said status outputs by said logic circuit means, said logic circuit means applies an output to said interruption request input whereby said CPU means is reset to its initial state just after power is applied to said system; and (c) said interruption request input of said CPU means being a top-level priority input and being non-maskable.
Claim 2
Dependent Claim
120 words
A fail-safe computer system for vehicle control, said system comprising: (a) a CPU means having at least two CPU status information outputs and an interruption request input; (b) a detecting logic circuit means having the inputs thereof coupled to said status information outputs and having the output thereof coupled to said interruption request input, wherein upon detection of a HALT signal at any of said status outputs by said logic circuit means, said logic circuit means applies an output to said interruption request input whereby said CPU means is reset to its initial state just after power is applied to said system; and (c) said interruption request input of said CPU means being a top-level priority input and being non-maskable.
Claim 3
Dependent Claim
20 words
A fail-safe computer system as set forth in claim 1, wherein said detecting logic circuit means is a NOR gate.
Claim 4
Dependent Claim
54 words
A fail-safe computer system as set forth in claim 1, wherein said system includes a memory and wherein said CPU means generates a JUMP instruction for addressing said memory to a specific address in response to an output from said logic circuit means being applied to said interruption request input of said CPU means.
Claim 5
Dependent Claim
25 words
A fail-safe computer system as set forth in claim 3, wherein said specific address is the initial address after power is applied to said system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |