Patent US4587638A successfully refreshed from Google Patents.
US4587638A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1984-07-12
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Granted: 1986-05-06
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Expires: 2004-07-12
Abstract
Abstract In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.
Inventors
- 👤 Mitsuo Isobe
- 👤 Takayasu Sakurai
- 👤 Kazuhiro Sawada
- 👤 Tetsuya Iizuka
- 👤 Takayuki Ohtani
- 👤 Akira Aono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:35
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C29/83; G11C29/832
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
182 words
A semiconductor memory device comprising: memory cells, arranged in rows, for storing data; a plurality of select lines, each of which is connected to the memory cells in a different one of said rows; first selecting means for receiving an address signal and for setting a predetermined voltage on one of said plurality of select lines corresponding to the contents of said address signal, thereby to place said one select line at a select level; redundant memory cells arranged in rows; at least one redundancy select line which is commonly connected to said redundant memory cells arranged in the same row; programmable redundancy selecting means for receiving said address signal and for placing said redundancy select line at a select level designated by said address signal; cuttable fuse elements individually connected between said first selecting means and a different one of said select lines; and load means connected between said select lines and a predetermined voltage for maintaining the voltage on a select line at a non-select level different from said select level if said corresponding select line fuse element is cut.
Claim 2
Dependent Claim
182 words
A semiconductor memory device comprising: memory cells, arranged in rows, for storing data; a plurality of select lines, each of which is connected to the memory cells in a different one of said rows; first selecting means for receiving an address signal and for setting a predetermined voltage on one of said plurality of select lines corresponding to the contents of said address signal, thereby to place said one select line at a select level; redundant memory cells arranged in rows; at least one redundancy select line which is commonly connected to said redundant memory cells arranged in the same row; programmable redundancy selecting means for receiving said address signal and for placing said redundancy select line at a select level designated by said address signal; cuttable fuse elements individually connected between said first selecting means and a different one of said select lines; and load means connected between said select lines and a predetermined voltage for maintaining the voltage on a select line at a non-select level different from said select level if said corresponding select line fuse element is cut.
Claim 3
Dependent Claim
74 words
A semiconductor memory device according to claim 1, wherein said first selecting means comprises: select signal generating means for inputting said address signal and outputting a select signal corresponding to said address signal; and a transistor circuit connected to said select signal generating means and to each of said fuse elements, said transistor circuit being combined with said load means and operating as an inverter circuit when said fuse elements are not cut off.
Claim 4
Dependent Claim
15 words
A semiconductor memory device according to claim 1, wherein said load means includes resistor elements.
Claim 5
Dependent Claim
15 words
A semiconductor memory device according to claim 1, wherein said load means includes MOS transistors.
Claim 6
Dependent Claim
25 words
A semiconductor memory device according to claim 1, wherein said load means includes a plurality of elements connected at several locations on said select lines.
Claim 7
Dependent Claim
102 words
A semiconductor memory device according to claim 1, wherein each of said rows of memory cells is divided into a plurality of sections, and wherein said select lines include first select lines provided in each of said sections and being connected to said first selecting means, each of said first select lines being commonly connected to said memory cells in the same section; and second select lines which are provided for every one of said rows and are connected to said first selecting means, said fuse elements being individually connected between said first selecting means and each of said first select lines.
Claim 8
Dependent Claim
15 words
A semiconductor memory device according to claim 6, wherein said load means includes resistor elements.
Claim 9
Dependent Claim
15 words
A semiconductor memory device according to claim 6, wherein said load means includes MOS transistors.
Claim 10
Dependent Claim
71 words
A semiconductor memory device according to claim 6, wherein said first selecting means comprises: select signal generating means for inputting said address signal and outputting a select signal corresponding to said address signal; and a transistor circuit connected to said select signal generating means and said fuse elements, said transistor circuit being combined with said load means and operating as an inverter circuit when said fuse elements are not cut off.
Claim 11
Dependent Claim
110 words
A semiconductor memory device according to claim 1, wherein each of said rows of memory cells is divided into a plurality of sections, and wherein said select lines include first select lines provided in each of said sections and connected to said first selecting means, each of said first select lines being commonly connected to said memory cells in the same section; second select lines which are provided for every one of said rows and are connected to said first selecting means, said fuse elements being individually connected between said selecting means and each of said second select lines and said load means being connected to said second select lines.
Claim 12
Dependent Claim
15 words
A semiconductor memory device according to claim 10, wherein said load means includes resistor elements.
Claim 13
Dependent Claim
15 words
A semiconductor memory device according to claim 10, wherein said load means includes MOS transistors.
Claim 14
Dependent Claim
79 words
A semiconductor memory device according to claim 10, wherein said first selecting means comprises: select signal generating means for inputting said address signal and outputting a select signal corresponding to said address signal; and a transistor circuit connected to said select signal generating means, each of said select lines and each of said fuse elements, said transistor circuit being combined with said load means and operating as a NOR gate circuit when said fuse elements are not cut off.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |