Memory system

Claim 2

A memory system comprising: first and second memory blocks; first and second arithmetic devices; an addressing means for supplying a first addresss commonly to said first and second memory blocks; means for simultaneously reading out first and second data from said first memory block by said first address during a one memory access period; means for reading a third data from said second memory block by said first address during said one memory access period simultaneously with the reading out of said first and second data; and means for supplying said first and third data to said first arithmetic device and simultaneously supplying said second and third data to said second arithmetic device.

Claim 3

A memory system comprising: memory means having at least three memory banks each of which stores a plurality of data; an address register for storing an address; a decoder coupled to said address register and said memory means for decoding a part of said address stored in said address register to designate corresponding memory locations in said at least three memory banks; means responsive to said decoder for simultaneously reading the data in the memory locations of said at least three memory banks designated by said decoder; a first means coupled to said reading means for selecting one data from the at least three read-out data in response to another part of said address; means for adding a predetermined value to said another part of said address; a second means coupled to said reading means and said adding means for selecting another one data from said at least three read-out data in response to the added value of said another part of said address; means for transferring said one data and said another data selected by said first means and said second means to a utilization means; and utilization means for operating on said one data and said another data.

Claim 4

A memory system comprising: memory means having at least three memory banks each of which stores a plurality of data; an address register for storing an address; a decoder coupled to said address register and said memory means for decoding a part of said address stored in said address register to designate corresponding memory locations in said at least three memory banks; means responsive to said decoder for simultaneously reading the data in the memory locations of said at least three memory banks designated by said decoder; a first means coupled to said reading means for selecting one data from the at least three read-out data in response to another part of said address; means for adding a predetermined value to said another part of said address; a second means coupled to said reading means and said adding means for selecting another one data from said at least three read-out data in response to the added value of said another part of said address; means for transferring said one data and said another data selected by said first means and said second means to a utilization means; and utilization means for operating on said one data and said another data.

Claim 5

A memory system as claimed in claim 2 further comprising means coupled to said memory means for writing new data, during the period when said at least three data are read out of said memory means by said reading means, into the memory bank from which a data is read out by said reading means and not selected by said first and second means.

Claim 6

A memory system as claimed in claim 2, further comprising: another memory means having at least two memory banks each for storing a plurality of data; means responsive to a part of the address stored in said address register for designating a corresponding memory location in each of the at least two memory banks of said another memory means; means responsive to another part of the address stored in said address register for selecting one of said at least two memory banks of said another memory means; means for reading the data at the designated memory location of the selected one of said at least two memory banks; and means for transferring the data read from the designated memory location of the selected one of said at least two memory banks to said utilization means.

Claim 7

A memory as claimed in claim 4, further including writing means coupled to said another memory means for writing data into a memory bank of said another memory means not selected by the selecting means, while the data is read from the designated memory location of the selected one of said at least two memory banks.

Claim 8

A speech recognition system adapted to the dynamic pattern matching method in which a feature vector, a i , at point i, extracted from input speech information is compared against stored reference pattern, b j , at point j, for determining the feature vector which most closely corresponds to the reference pattern, said speech recognition system comprising: means for receiving feature vector data corresponding to input speech information; memory means for storing reference pattern data; a first memory array for receiving a plurlaity of said feature vectors; a second memory array for receiving at least one reference pattern; first write address means for write addressing said first memory array; second write address means for write addressing said second memory array; read address means for simultaneously read addressing said first and second memory arrays at a first address location in each memory array, said read address means including address incrementing means for read addressing a second address location in said first memory array, simultaneous with the read addressing of said first address location; first and second data register means associated with said first memory array; third data register means associated with said second memory array; means for transferring the feature vector data stored at said first address location in said first memory array to said first register means; means for transferring the feature vector data stored at said second address location in said second memory array to said second register means; means for transferring the reference pattern stored at said first address location in said second memory array to said third register means; and means for simultaneously comparing the reference pattern stored in said third register means with the feature vector data stored in said first register means and the feature vector data stored in said second register means.

Claim 9

A speech recognition system adapted to the dynamic pattern matching method in which a feature vector, a i , at point i, extracted from input speech information is compared against stored reference pattern, b j , at point j, for determining the feature vector which most closely corresponds to the reference pattern, said speech recognition system comprising: means for receiving feature vector data corresponding to input speech information; memory means for storing reference pattern data; a first memory array for receiving a plurlaity of said feature vectors; a second memory array for receiving at least one reference pattern; first write address means for write addressing said first memory array; second write address means for write addressing said second memory array; read address means for simultaneously read addressing said first and second memory arrays at a first address location in each memory array, said read address means including address incrementing means for read addressing a second address location in said first memory array, simultaneous with the read addressing of said first address location; first and second data register means associated with said first memory array; third data register means associated with said second memory array; means for transferring the feature vector data stored at said first address location in said first memory array to said first register means; means for transferring the feature vector data stored at said second address location in said second memory array to said second register means; means for transferring the reference pattern stored at said first address location in said second memory array to said third register means; and means for simultaneously comparing the reference pattern stored in said third register means with the feature vector data stored in said first register means and the feature vector data stored in said second register means.

Claim 10

The speech recognition system of claim 6, wherein said first memory array is comprised of N rows and M columns and said read address means includes, an address register means for designating both row and column address information, a first portion of the address in said address register designating column address information, a second portion of the address in said address register designating row address information, decoder means responsive to said first portion of the contents in said address register means for accessing common column locations in each row of said first memory array, first and second multiplexor means each receiving the data at the common column locations of the N rows of said first memory array designated by the first portion of the address in said address register means, said second portion of the address stored in said address register being inputted to said first multiplexor means and said address incrementing means, the output of said address incrementing means being connected to said second multiplexor means, the outputs from said first multiplexor means being connected to said first data register means, the outputs from said second multiplexor means being connected to said second data register means.

Claim 11

The speech recognition system of claim 7, wherein said means for simultaneously comparing the reference pattern with feature vector patterns stored in said first and second data registers is comprised of a first calculating means having inputs connected to the outputs of said first and third data registers and for calculating the distance d i , j between the feature vector a i and the reference pattern b j , and a second calculating means having inputs connected to the outputs of said second and third data registers and for calculating the distance d i+1 , j between the feature vector a i+1 and the reference pattern b j simultaneous with the calculation of the distance d i ,j.

Claim 12

The speech recognition system of claim 6, in which feature vectors occurring in the range j-r≦i≦j+r are compared to a reference pattern b j , said first memory array being comprised of 2 r+2 rows and M columns 2 r+1 rows storing feature vector data corresponding patterns a j-r , a j-r+1 , . . . a j , . . . a j+r to be compared to reference pattern b j , the 2 r+2 row storing the feature vector pattern a j+r+1 , said second memory array being comprised of at least two rows and M columns, said first row storing said referene pattern b j , said second row storing said reference pattern b j+1 against which is compared feature vectors in the range j-r+1≦i≦j+r+1.

Claim 13

In a speech recogniation system adapted for dynamic pattern matching, a method for determing distances d i ,j, d i+1 ,j+1, . . . d i+n , d j+n between feature vectors a i , a i+1 . . . a i+n where j-r≦i≦j+r and reference patterns b j , b j+1 , . . . b j+n comprising the steps of: providing a first memory array of 2 r+2 rows and M columns and storing 2 r+1 feature vectors in said first array; providing a second memory array of at least two rows and M columns; writing into said first array the feature vectors a i corresponding to a j-r , a j-r+1 , . . . a j , . . . a j+r ; writing into said second array the reference pattern b j ; simultaneously reading two feature vectors a i and a i+1 and the reference pattern b j out of said first and second memory arrays; and simultaneously calculating the distances d i ,j from the vector a i and reference b j and d i+1 ,j from the vector a i+1 and the reference b j .

Claim 14

In a speech recogniation system adapted for dynamic pattern matching, a method for determing distances d i ,j, d i+1 ,j+1, . . . d i+n , d j+n between feature vectors a i , a i+1 . . . a i+n where j-r≦i≦j+r and reference patterns b j , b j+1 , . . . b j+n comprising the steps of: providing a first memory array of 2 r+2 rows and M columns and storing 2 r+1 feature vectors in said first array; providing a second memory array of at least two rows and M columns; writing into said first array the feature vectors a i corresponding to a j-r , a j-r+1 , . . . a j , . . . a j+r ; writing into said second array the reference pattern b j ; simultaneously reading two feature vectors a i and a i+1 and the reference pattern b j out of said first and second memory arrays; and simultaneously calculating the distances d i ,j from the vector a i and reference b j and d i+1 ,j from the vector a i+1 and the reference b j .

Claim 15

The method for determining distances d i ,j, d i+1 , j+1 , . . . d i+n , j+n according to claim 10, further including the steps of: writing the feature vector a j+1+r into the 2 r+2 row of said first memory array, writing the reference pattern b j+1 into the second row of the second memory array; and reading two feature vectors a i and a i+1 where j-r≦i≦j+r-1 and reference pattern b j simultaneously with the writing of feature vector j+1+r into first memory array and the writing of the reference pattern b j+1 into the second memory array.