Patent US4587612A successfully refreshed from Google Patents.
US4587612A
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Accelerated instruction mapping external to source and target instruction streams for near realtime injection into the latter
Assignee: International Business Machines Corp
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Filing: 1982-10-22
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Granted: 1986-05-06
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Expires: 2002-10-22
Abstract
Abstract If a predetermined field (FIG. 3/27) within a source instruction indexes and accesses a body of control information from memory (FIG. 2/5), and if control information (FIG. 4) designates the field-to-field (register-to-register) mapping (FIG. 6), then a skeleton target instruction (FIG. 3/29; FIG. 4) can be filled in by either selectively copying the fields of the source instruction or otherwise computing same. If the mapping is executed by an interposed independent processor then overlapping of such conversion enhances throughput, the independent processor converting multifield instructions for a CPU of a first kind to multifield instructions for a CPU of a second kind without disrupting the logical flow or execution of either source or target instruction streams.
Inventors
- 👤 Dale E. Fisk
- 👤 Robert L. Griffith
- 👤 Merle E. Homan
- 👤 George Radin
- 👤 Waldo J. Richards
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/30174; G06F9/38; G06F9/3877; G06F9/3879; G06F9/44; G06F9/455; G06F9/45504; G06F9/45533; G06F9/45554
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
72 words
A method for converting a source CPU multifield instruction obtained from memory as data into one or more target CPU multifield instructions; comprising the steps of: fetching a microinstruction and at least one skeleton target instruction from the memory under control of said source instruction; and filling in the skeleton target instruction according to the microinstruction contents by copying or computing from selected fields of said source instruction into the skeleton instruction.
Claim 2
Independent Claim
72 words
A method for converting a source CPU multifield instruction obtained from memory as data into one or more target CPU multifield instructions; comprising the steps of: fetching a microinstruction and at least one skeleton target instruction from the memory under control of said source instruction; and filling in the skeleton target instruction according to the microinstruction contents by copying or computing from selected fields of said source instruction into the skeleton instruction.
Claim 3
Dependent Claim
42 words
A method according to claim 1 wherein each fetched microinstruction includes an address portion which, if non-zero, designates a memory location of a successive microinstruction to be fetched from the memory or, if zero, indicates termination of the microinstruction code word sequence.
Claim 4
Dependent Claim
20 words
A method according to claim 1, wherein the steps of fetching and filling in are performed in time overlap relation.
Claim 5
Dependent Claim
27 words
A method according to claim 1, wherein the method comprises the additional step of inserting said filled-in target instruction directly into the executable target CPU instruction stream.
Claim 6
Dependent Claim
102 words
A translator for use with a dual cache processing unit for converting instructions stored in the first of two caches as data into counterpart code words executable by the processing unit, the translator comprising: means for fetching an instruction from the first cache; means for fetching a microinstruction and a skeleton code word from the second cache at a location determined by the operating code portion of the fetched instruction; and means for filling in the skeleton code word according to the microinstruction with the fields of the fetched instruction and applying the filled-in code word to the processing unit for execution.
Claim 7
Dependent Claim
102 words
A translator for use with a dual cache processing unit for converting instructions stored in the first of two caches as data into counterpart code words executable by the processing unit, the translator comprising: means for fetching an instruction from the first cache; means for fetching a microinstruction and a skeleton code word from the second cache at a location determined by the operating code portion of the fetched instruction; and means for filling in the skeleton code word according to the microinstruction with the fields of the fetched instruction and applying the filled-in code word to the processing unit for execution.
Claim 8
Dependent Claim
52 words
A translator according to claim 5, characterized in that the means for fetching an instruction from the first cache and the means for fetching the microinstructions and a skeleton code word each include means for cycle steal accessing the second cache and cycle steal accessing instruction execution cycles of the processing unit.
Claim 9
Independent Claim
137 words
An apparatus for format-converting multi field source instructions stored in a data cache into target instructions and inserting them into an instruction stream obtained from an instruction cache without otherwise perturbing target machine instruction execution, comprising: a first and a second register; means for accessing the data cache and loading a source instruction into said first register, said source instruction including an OP field; means responsive to the OP field contents within said first register for cycle steal accessing the instruction cache and loading a control word into the second register; mapping logic conditioned by the control word in the second register for selectively copying or gating out source instruction fields from the first register into the target instruction; and means for cycle stealing the target machine and merging the formatted target instruction into the instruction stream.
Claim 10
Independent Claim
137 words
An apparatus for format-converting multi field source instructions stored in a data cache into target instructions and inserting them into an instruction stream obtained from an instruction cache without otherwise perturbing target machine instruction execution, comprising: a first and a second register; means for accessing the data cache and loading a source instruction into said first register, said source instruction including an OP field; means responsive to the OP field contents within said first register for cycle steal accessing the instruction cache and loading a control word into the second register; mapping logic conditioned by the control word in the second register for selectively copying or gating out source instruction fields from the first register into the target instruction; and means for cycle stealing the target machine and merging the formatted target instruction into the instruction stream.
Claim 11
Dependent Claim
138 words
In combination with at least one source and one target CPU of dissimilar executable instruction formats, an apparatus for translating multifield instructions from the source into a target CPU format and for injecting the translated instructions into the directly executable target CPU instruction stream, each source instruction having at least one OP field, comprising: memory means; means reponsive to each multifield source instruction for fetching a body of control information and skeleton target instructions from said memory means at a location indexed by the source instruction OP field; means for filling in the fields of the fetched skeleton target instructions by either selectively copying source instruction fields or otherwise computing their contents according to the fetched body of control information; and means for merging the filled in target instructions into the executable instruction stream of the target CPU.
Claim 12
Dependent Claim
138 words
In combination with at least one source and one target CPU of dissimilar executable instruction formats, an apparatus for translating multifield instructions from the source into a target CPU format and for injecting the translated instructions into the directly executable target CPU instruction stream, each source instruction having at least one OP field, comprising: memory means; means reponsive to each multifield source instruction for fetching a body of control information and skeleton target instructions from said memory means at a location indexed by the source instruction OP field; means for filling in the fields of the fetched skeleton target instructions by either selectively copying source instruction fields or otherwise computing their contents according to the fetched body of control information; and means for merging the filled in target instructions into the executable instruction stream of the target CPU.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |