Patent US4587494A successfully refreshed from Google Patents.
US4587494A
Expired / Lapsed
US
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Quasi-complementary class B IC output stage
Assignee: National Semiconductor Corp
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Filing: 1985-01-17
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Granted: 1986-05-06
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Expires: 2005-01-17
Abstract
Abstract A class B IC transistor output stage, using a pair of NPN transistors, is described. A quasi-complementary transistor is employed to establish the stage quiescent bias. An NPN bias transistor is coupled to the output sink transistor and is driven from the emitter of the input driver transistor. Therefore, the input signal is coupled to apply the signal directly to the base of the sink transistor as well as to the source transistor. This feedforward arrangement by-passes the PNP transistor when a signal is applied so that the asymmetrical performance of the PNP transistor does not adversely affect the signal performance.
Inventors
- 👤 Robert J. Widlar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:26
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3069; H03F3/3071; H03F3/3072
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
166 words
A class B integrated circuit output circuit having an input terminal, an output terminal, and first and second supply terminals connectable to a source of operating power, said circuit comprising: first and second transistor means having a first polarity, each having a base and having their emitter-collector circuits coupled in series across said first and second supply terminals whereby the juncture of said first and second transistor means comprises said output terminal; third transistor means having said first polarity with its collector coupled to said base of said second transistor means, its emitter coupled to said second supply terminal and its base coupled to a source of bias potential; fourth transistor means having said first polarity with its emitter coupled to said emirter of said third transistor means, its collector coupled to said base of said first transistor means, and its base coupled to said circuit input terminal; and means for forcing said third transistor means to operate as a diode at the higher signal frequencies.
Claim 2
Dependent Claim
166 words
A class B integrated circuit output circuit having an input terminal, an output terminal, and first and second supply terminals connectable to a source of operating power, said circuit comprising: first and second transistor means having a first polarity, each having a base and having their emitter-collector circuits coupled in series across said first and second supply terminals whereby the juncture of said first and second transistor means comprises said output terminal; third transistor means having said first polarity with its collector coupled to said base of said second transistor means, its emitter coupled to said second supply terminal and its base coupled to a source of bias potential; fourth transistor means having said first polarity with its emitter coupled to said emirter of said third transistor means, its collector coupled to said base of said first transistor means, and its base coupled to said circuit input terminal; and means for forcing said third transistor means to operate as a diode at the higher signal frequencies.
Claim 3
Dependent Claim
57 words
The circuit of claim 1 including fifth transistor means having a complementary polarty with its collector coupled to said base of said second transistor means and its base coupled to said collector of said fourth transistor means whereby said second and fifth transistor means in combination provides quasi-complementrary transistor means with respect to said first transistor means.
Claim 4
Dependent Claim
44 words
The circuit of claim 1 wherein said emitters of said third and fourth transistor means are coupled to said second supply terminal by current conducting means whereby said fourth transistor means acts as an emitter-follower to drive said emitter of said third transistor means.
Claim 5
Dependent Claim
48 words
The circuit of claim 3 in further combination with a clamping diode means having one terminal coupled to said collector of said third transistor means and its other terminal coupled to a source of clamping potential selected to prevent said third transistor means from being driven into saturation.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |