US4587491A
Expired / Lapsed
US
⏱️ 0.0 years remaining
IC class AB amplifier output stage
Assignee: National Semiconductor Corp
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Filing: 1985-04-29
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Granted: 1986-05-06
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Expires: 2005-04-29
Abstract
Abstract A class AB monolithic silicon IC output stage is shown wherein the main output transistors are NPN structures. The current sourcing transistor is provided with an additional scaled down reference emitter and the two emitters connected to the inputs of an op amp which has its output coupled to drive the current sink transistor. The base of the current source transistor is driven from a high gain driver transistor stage which may also contain a d-c level shifter that permits the inclusion of a complementary current sink transistor that can greatly reduce cross-over distortion while conducting only quiescent current.
Inventors
- 👤 Matsuro Koterasawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:31
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/32; H03F1/3217; H03F3/00; H03F3/30; H03F3/3083; H03F3/3084
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
152 words
An integrated output stage circuit having an input and output terminals and first and second power supply terminals connectable to a source of operating power, said circuit comprising: a source NPN transistor having its emitter coupled to said output terminal, its collector coupled to said first power supply termial and a base; a source reference NPN transistor having its collector and base terminals coupled to like elements in said source NPN transistor and an emitter; a sink NPN transistor having its collector coupled to said output terminal, its emitter coupled to said second power supply terminal, and a base; an operational amplifier having its non-inverting input coupled to said emitter of said source NPN transistor, its inverting input coupled to said emitter of said source reference transistor and its output coupled to said base of said sink NPN transistor; and signal drive means coupled to said base of said source NPN transistor.
Claim 2
Dependent Claim
152 words
An integrated output stage circuit having an input and output terminals and first and second power supply terminals connectable to a source of operating power, said circuit comprising: a source NPN transistor having its emitter coupled to said output terminal, its collector coupled to said first power supply termial and a base; a source reference NPN transistor having its collector and base terminals coupled to like elements in said source NPN transistor and an emitter; a sink NPN transistor having its collector coupled to said output terminal, its emitter coupled to said second power supply terminal, and a base; an operational amplifier having its non-inverting input coupled to said emitter of said source NPN transistor, its inverting input coupled to said emitter of said source reference transistor and its output coupled to said base of said sink NPN transistor; and signal drive means coupled to said base of said source NPN transistor.
Claim 3
Dependent Claim
127 words
An integrated output stage circuit having an input and output terminals and first and second power supply terminals connectable to a source of operating power, said circuit comprising: a dual emitter NPN transistor having its collector coupled to said first power supply terminal, a base, a source emitter coupled to said output terminal and a reference emitter; a sink NPN transistor having its collector coupled to said output terminal, its emitter coupled to said second power supply terminal, and a base; an operational amplifier having its non-inverting input coupled to said source emitter, its inverting input coupled to said reference emitter and its output coupled to said base of said sink NPN transistor; and signal drive means coupled to said base of said dual emitter NPN transistor.
Claim 4
Dependent Claim
127 words
An integrated output stage circuit having an input and output terminals and first and second power supply terminals connectable to a source of operating power, said circuit comprising: a dual emitter NPN transistor having its collector coupled to said first power supply terminal, a base, a source emitter coupled to said output terminal and a reference emitter; a sink NPN transistor having its collector coupled to said output terminal, its emitter coupled to said second power supply terminal, and a base; an operational amplifier having its non-inverting input coupled to said source emitter, its inverting input coupled to said reference emitter and its output coupled to said base of said sink NPN transistor; and signal drive means coupled to said base of said dual emitter NPN transistor.
Claim 5
Dependent Claim
25 words
The circuit of claim 2 wherein said dual emitter NPN transistor involves ratioed emitters and said reference emitter is the smaller of the two emitters.
Claim 6
Dependent Claim
28 words
The circuit of claim 1 wherein said operational amplifier includes inputs that require an operating current that can be controlled to establish the quiescent current of said circuit.
Claim 7
Dependent Claim
39 words
The circuit of claims 1 or 2 further comprising a PNP sink transistor having an emitter coupled to said output terminal, a collector coupled to said second power supply terminal and a base coupled to said signal drive means.
Claim 8
Dependent Claim
38 words
The circuit of claim 5 wherein said signal drive means contains level shifting means whereby said PNP sink transistor is driven at a level that is two junction diode voltages below said base of said source NPN transistor.
Claim 9
Dependent Claim
40 words
The circuit of claims 1 or 2 wherein said operational amplifier includes an input stage in which a pair of PNP transistors are operated as common base connected devices whereby the input signal must include a direct current biasing component.
Claim 10
Dependent Claim
39 words
The circuit of claim 7 wherein said input stage PNP transistors are plural collector devices and one collector in each transistor is returned to its base and to a constant current sink which determines said direct current biasing component.
Claim 11
Dependent Claim
20 words
The circuit of claim 8 wherein resistors are coupled in series with the emitters of said pair of PNP transistors.
References Cited (Backward Citations)
US3974456A
Cited
US4316149A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |