US3974456A
Expired / Lapsed
US
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Amplifier output stage
Assignee: National Semiconductor Corp
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Filing: 1975-02-12
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Granted: 1976-08-10
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Expires: 1995-02-12
Abstract
Abstract An output stage for an amplifier operating under capacitive loading conditions includes an FET-bipolar composite connected between its input and its output and an emitter follower connected in parallel with the FET. A current source and current tracking circuit maintains the emitter follower conductive at all times, such that relatively high frequency input signals are supplied to the output through the emitter follower. When the output stage is sourcing current to the load, the signal path is through the emitter follower. When the output stage is sinking current from the load, the signal path is primarily through the FET when relatively low frequency input signals are connected thereto and the signal path is primarily through the emitter follower when relatively high frequency input signals are connected thereto.
Inventors
- 👤 Ronald W. Russell
- 👤 Kyle M. Black
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:09
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3083; H03F3/3086; H03F3/3089; H03F1/00; H03F1/42; H03F3/50
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
91 words
An amplifier output stage having at least an input and an output terminal, said stage comprising: a current sinking transistor having one of its collector and emitter coupled to said output terminal; an FET coupled between said output terminal and the base of said transistor; means for supplying an input signal to the gate of said FET; means for maintaining the gate-source voltage of said FET constant; and a first emitter-follower having its base coupled to said input terminal and one of its emitter and collector coupled to said output terminal.
Claim 2
Dependent Claim
91 words
An amplifier output stage having at least an input and an output terminal, said stage comprising: a current sinking transistor having one of its collector and emitter coupled to said output terminal; an FET coupled between said output terminal and the base of said transistor; means for supplying an input signal to the gate of said FET; means for maintaining the gate-source voltage of said FET constant; and a first emitter-follower having its base coupled to said input terminal and one of its emitter and collector coupled to said output terminal.
Claim 3
Dependent Claim
51 words
The amplifier output stage of claim 1, wherein said maintaining means includes a first current source having a current therethrough which is proportional to the I DSS of said FET, and a current mirror having one branch thereof connected to said current source and the other branch connected to said FET.
Claim 4
Dependent Claim
56 words
The amplifier output stage of claim 2, wherein said supplying means includes a diode coupled between said input terminal and the gate of said FET, said diode and said first emitter-follower being matched such that their currents are equal when the voltage drop across aid diode is equal to the base-emitter voltage of said first emitter-follower.
Claim 5
Dependent Claim
55 words
The amplifier output stage of claim 3 further including a second-emitter-follower for connecting said input terminal to said diode and to said first emitter-follower, said second emitter-follower having its base coupled to said input terminal and having one of its collector and emitter coupled to said diode and to the base of said first emitter-follower.
Claim 6
Dependent Claim
33 words
The amplifier output stage of claim 4 further comprising a second current source connected in parallel with the serial combination of said first current source and said one branch of said current mirror.
Claim 7
Dependent Claim
34 words
The amplifier output stage of claim 4, further comprising a second current source connected in parallel with said first current source and said one branch of said current mirror in series with one another.
References Cited (Backward Citations)
US3776410A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-10 | 1980-02-09 | 1980-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-10 | 1984-02-09 | 1984-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-10 | 1988-02-09 | 1988-08-10 | $7700.00 | Window Closed / Lapsed |