Delay testing method for CMOS LSI and VLSI integrated circuits

Claim 1

A method of performing delay testing of CMOS LSI or VLSI integrated circuits comprising the steps of: (a) realizing a shift register circuit having a large number of serially connected stages as part of the LSI/VLSI CMOS circuitry; (b) realizing a shift register control circuit as part of the LSI/VLSI CMOS circuitry that controls the operation of said shift register circuit and allows the shift register circuit to operate in at least one of two modes, a first mode of which permits data signals to be controllably clocked through the shift register stages, and a second mode of which allows the shift register to operate as a ring oscillator and permits data signals to propagate through the shift register stages at a speed limited only by the inherent propagation delay times associated with each shift register stage; (c) including logic combinational circuitry as part of said LSI/VLSI circuitry that selectively allows said shift register circuit to be configured as a ring oscillator in response to control signals generated by said shift register control circuit; (d) placing input/output pads around the periphery of said LSI/VLSI CMOS circuitry through which data signals and control signals may be sent to or received from the shift register circuit, control circuit, and other circuitry forming part of said LSI/VLSI circuitry; (e) sending appropriate control signals to said shift register control circuit to cause said shift register circuit to assume its second mode of operation; (f) injecting a data signal into a first stage to said shift register circuit through one of said input/output pads; and (g) measuring the period of oscillation associated with said ring oscillator, said period of oscillation being related to the delay time it takes said data signal to propagate through the stages of said shift register circuit.

Claim 2

A method of performing delay testing of CMOS LSI or VLSI integrated circuits comprising the steps of: (a) realizing a shift register circuit having a large number of serially connected stages as part of the LSI/VLSI CMOS circuitry; (b) realizing a shift register control circuit as part of the LSI/VLSI CMOS circuitry that controls the operation of said shift register circuit and allows the shift register circuit to operate in at least one of two modes, a first mode of which permits data signals to be controllably clocked through the shift register stages, and a second mode of which allows the shift register to operate as a ring oscillator and permits data signals to propagate through the shift register stages at a speed limited only by the inherent propagation delay times associated with each shift register stage; (c) including logic combinational circuitry as part of said LSI/VLSI circuitry that selectively allows said shift register circuit to be configured as a ring oscillator in response to control signals generated by said shift register control circuit; (d) placing input/output pads around the periphery of said LSI/VLSI CMOS circuitry through which data signals and control signals may be sent to or received from the shift register circuit, control circuit, and other circuitry forming part of said LSI/VLSI circuitry; (e) sending appropriate control signals to said shift register control circuit to cause said shift register circuit to assume its second mode of operation; (f) injecting a data signal into a first stage to said shift register circuit through one of said input/output pads; and (g) measuring the period of oscillation associated with said ring oscillator, said period of oscillation being related to the delay time it takes said data signal to propagate through the stages of said shift register circuit.