US4586128A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arbitrator circuit and technique for use in a digital computing system having multiple bus controllers
Assignee: Unisys Corp
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Filing: 1983-04-14
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Granted: 1986-04-29
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Expires: 2003-04-14
Abstract
Abstract In a digital computing system having multiple controllers, multiple memories and multiple memory interfaces, wherein each controller periodically requests access to a memory, an arbitrator device in the memory interfaces is disclosed, which includes circuitry for granting poll requests of the controllers in a prescribed manner of protocol. The arbitrator of this invention includes an input gating structure, a priority encoder, a poll request register and a grant register. During an arbitration cycle, upon reception of one or more active poll signals from the bus controllers, the respective grant signal of the highest priority active poll is immediately returned to the controller. All non-granted poll inputs are disabled so as to lock out any subsequent poll signals. This provides the granted controller exclusive use and control of the data bus between the controller and the memory interface.
Inventors
- 👤 Dale S. DeWoskin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:14
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F13/36; G06F13/362; G06F13/364
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
295 words
In a digital computing system having multiple controllers of a type where each controller periodically sends request signals to access a memory, an arbitrator device for receiving the request signals and for generating grant signals which permit access of the controllers to said memory one at a time, saod arbitrator comprising: an input gating structure means for receiving said grant signals and said request signals from the controllers on a set of input terminals and for passing each received request signal to a respective output terminal subject to a respective condition, the condition being that a request signal from any one particular controller is inhibited from passing by a grant signal to any other controller; a priority encoder means for selecting one request signal at a time in accordance with a prescribed manner of protocol from those request signals that are passed to the output terminals of said input gating structure means; said priority encoder having input terminals coupled to said output terminals of said input gating structure means; a request register means having input terminals coupled to output terminals of said priority encoder means, for storing the one request signal selected by said priority encoder means; a first ORing means for generating signals as the logical OR of the one request signal stored in said request register means with the one request signal selected by said priority encoder means; a grant register means having input terminals coupled to said first ORing means for storing the logical OR signal therefrom; and a second ORing means for supplying said grant signals to said controllers and to said input gating structure as the logical OR of said logical OR signal stored in said grant register means with the one request signal selected by said priority encoder means.
Claim 2
Dependent Claim
295 words
In a digital computing system having multiple controllers of a type where each controller periodically sends request signals to access a memory, an arbitrator device for receiving the request signals and for generating grant signals which permit access of the controllers to said memory one at a time, saod arbitrator comprising: an input gating structure means for receiving said grant signals and said request signals from the controllers on a set of input terminals and for passing each received request signal to a respective output terminal subject to a respective condition, the condition being that a request signal from any one particular controller is inhibited from passing by a grant signal to any other controller; a priority encoder means for selecting one request signal at a time in accordance with a prescribed manner of protocol from those request signals that are passed to the output terminals of said input gating structure means; said priority encoder having input terminals coupled to said output terminals of said input gating structure means; a request register means having input terminals coupled to output terminals of said priority encoder means, for storing the one request signal selected by said priority encoder means; a first ORing means for generating signals as the logical OR of the one request signal stored in said request register means with the one request signal selected by said priority encoder means; a grant register means having input terminals coupled to said first ORing means for storing the logical OR signal therefrom; and a second ORing means for supplying said grant signals to said controllers and to said input gating structure as the logical OR of said logical OR signal stored in said grant register means with the one request signal selected by said priority encoder means.
Claim 3
Dependent Claim
23 words
An arbitrator as in claim 1 further including means for selecting said arbitrator as a master unit in a group of interconnected arbitrators.
Claim 4
Dependent Claim
32 words
An arbitrator as in claim 1 further including means for generating a ready signal for transmission to a requesting controller that has been granted access when an arbitration cycle has been completed.
Claim 5
Dependent Claim
31 words
An arbitrator as in claim 1 in combination with means for generating an arbitrator unlocking signal to said input gating structure means in response to said request signal from said controllers.
Claim 6
Dependent Claim
333 words
In a digital computing system having multiple controllers, multiple memories and multiple interface circuits to each of said memories with each controller being of a type which periodically sends request signals to access a memory, an arbitrator device in each of said interface circuits for receiving the request signals and for generating grant signals which permit access of the controllers to said memories in a prescribed manner of protocol, each of said arbitrators comprising: means for selecting one of said arbitrators as a master unit and disabling the remaining arbitrators; an input gating structure means for receiving said grant signals and said request signals from the controllers on a set of input terminals and for passing each received request signal to a respective output terminal subject to a respective condition, the condition being that a request signal from any one particular controller is inhibited from passing by a grant signal to any other controller; a priority encoder means for selecting one request signal at a time in accordance with a prescribed manner of protocol from those request signals that are passed to the output terminals of said input gating structure means; said priority encoder having input terminals coupled to said output terminals of said input gating structure means; a request register means having input terminals coupled to output terminals of said priority encoder means, for storing the one request signal selected by said priority encoder means; a first ORing means for generating signals as the logical OR of the one request signal stored in said request register means with the one request signal selected by said priority encoder means; a grant register means having input terminals coupled to said first ORing means for storing the logical OR signal therefrom; and a second ORing means for supplying said grant signals to said controllers and to said input gating structure as the logical OR of said logical OR signal stored in said grant register means with one request signal selected by said priority encoder means.
Claim 7
Dependent Claim
333 words
In a digital computing system having multiple controllers, multiple memories and multiple interface circuits to each of said memories with each controller being of a type which periodically sends request signals to access a memory, an arbitrator device in each of said interface circuits for receiving the request signals and for generating grant signals which permit access of the controllers to said memories in a prescribed manner of protocol, each of said arbitrators comprising: means for selecting one of said arbitrators as a master unit and disabling the remaining arbitrators; an input gating structure means for receiving said grant signals and said request signals from the controllers on a set of input terminals and for passing each received request signal to a respective output terminal subject to a respective condition, the condition being that a request signal from any one particular controller is inhibited from passing by a grant signal to any other controller; a priority encoder means for selecting one request signal at a time in accordance with a prescribed manner of protocol from those request signals that are passed to the output terminals of said input gating structure means; said priority encoder having input terminals coupled to said output terminals of said input gating structure means; a request register means having input terminals coupled to output terminals of said priority encoder means, for storing the one request signal selected by said priority encoder means; a first ORing means for generating signals as the logical OR of the one request signal stored in said request register means with the one request signal selected by said priority encoder means; a grant register means having input terminals coupled to said first ORing means for storing the logical OR signal therefrom; and a second ORing means for supplying said grant signals to said controllers and to said input gating structure as the logical OR of said logical OR signal stored in said grant register means with one request signal selected by said priority encoder means.
Claim 8
Dependent Claim
32 words
An arbitrator as in claim 5 further including means for generating a ready signal for transmission to a requesting controller that has been granted access when an arbitration cycle has been completed.
Claim 9
Dependent Claim
31 words
An arbitrator as in claim 5 in combination with means for generating an arbitrator unlocking signal to said input gating structure means in response to said request signals from said controllers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |