Patent US4585001A successfully refreshed from Google Patents.
US4585001A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cardiac pacer signal detector
Assignee: Norland Corp
•
Filing: 1984-01-23
•
Granted: 1986-04-29
•
Expires: 2004-01-23
Abstract
Abstract A battery powered external pacer operable in fixed-rate and demand modes includes a sense amplifier having an active notch filter system for attenuating power line interference. The filter system comprises four separate data channels each including a transmission gate synchronously driven by pacer clock pulses for frequency stability. Charges developed on capacitors in each data channel are summed by an output capacitor to avoid the need for amplifiers in each channel. A detector having two comparators for detecting positive and negative directed R-wave components derives heart pulses from the amplified signal. A pulse-driven reference supply having very low power consumption provides operating bias required by the detector. A battery monitor having a single comparator simultaneously monitors supply voltage for low and unusable voltage levels.
Inventors
- 👤 Kenneth W. Belt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:02
CPC Classifications
A; A61; A61N; A61N1/00; A61N1/18; A61N1/32; A61N1/36; A61N1/362; A61N1/365; A61N1/37; A61N1/3718
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
256 words
A detector circuit for detecting the occurrence of a desired sensed cardiac signal component in the presence of extraneous noise components in a cardiac sensing channel of a cardiac pacer, wherein the absolute amplitude of the desired cardiac signal component exceeds a predetermined threshold level greater than the absolute amplitude level of the extraneous noise component, comprising: a first differential amplifier having inverting and non-inverting inputs; a second differential amplifier having inverting and non-inverting inputs; means for applying said sensed cardiac signal component and said noise components to said inverting input of said first differential amplifier, and to said non-inverting input of said second differential amplifier; bias means for applying a first bias at a first predetermined voltage level to said non-inverting input of said first differential amplifier and for applying a second bias at a second predetermined voltage level to said non-inverting input of said second differential amplifier; reference voltage means for applying a reference voltage at a third predetermined voltage level greater than each of said first and second predetermined voltage levels to each of said inverting inputs whereby said first differential amplifier produces an output upon said signal component exceeding the difference between said first bias and reference voltage levels in one direction, and said second differential amplifier produces an output upon said signal component exceeding the difference between said second bias and reference voltage levels in the other direction; and means for combining the outputs of said first and second differential amplifiers to form an output signal indicative of said signal component.
Claim 2
Dependent Claim
256 words
A detector circuit for detecting the occurrence of a desired sensed cardiac signal component in the presence of extraneous noise components in a cardiac sensing channel of a cardiac pacer, wherein the absolute amplitude of the desired cardiac signal component exceeds a predetermined threshold level greater than the absolute amplitude level of the extraneous noise component, comprising: a first differential amplifier having inverting and non-inverting inputs; a second differential amplifier having inverting and non-inverting inputs; means for applying said sensed cardiac signal component and said noise components to said inverting input of said first differential amplifier, and to said non-inverting input of said second differential amplifier; bias means for applying a first bias at a first predetermined voltage level to said non-inverting input of said first differential amplifier and for applying a second bias at a second predetermined voltage level to said non-inverting input of said second differential amplifier; reference voltage means for applying a reference voltage at a third predetermined voltage level greater than each of said first and second predetermined voltage levels to each of said inverting inputs whereby said first differential amplifier produces an output upon said signal component exceeding the difference between said first bias and reference voltage levels in one direction, and said second differential amplifier produces an output upon said signal component exceeding the difference between said second bias and reference voltage levels in the other direction; and means for combining the outputs of said first and second differential amplifiers to form an output signal indicative of said signal component.
Claim 3
Dependent Claim
86 words
A detector circuit as defined in claim 2 wherein said circuit includes a source of operating voltage, and said bias means comprise first, second and third serially connected resistances connected between said source of operating voltage and ground, said first bias being developed at the juncture of said first and second resistances and said second bias being developed at the juncture of said second and third resistances such that the difference between said first and second biases is dependent on the resistance of said second resistance.
Claim 4
Dependent Claim
55 words
A detector as defined in claim 2, said reference voltage means further comprising a source of reference voltage and a voltage divider connected between said source of operating voltage, said source of reference voltage and ground for combining said reference voltage with a portion of the operating voltage to establish said third predetermined voltage level.
References Cited (Backward Citations)
US3528428A
Cited
US3611164A
Cited
US3725795A
Cited
US4184493A
Cited
US4173221A
Cited
US4345169A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |