US4584762A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Lateral transistor separated from substrate by intersecting slots filled with substrate oxide for minimal interference therefrom and method for producing same
Assignee: Conexant Systems LLC
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Filing: 1983-12-05
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Granted: 1986-04-29
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Expires: 2003-12-05
Abstract
Abstract The invention is a transistor or array thereof and method for producing same in VLSI dimensions on a silicon substrate doped P or N type by forming intersecting slots in spaced apart relation across the substrate to define semiarrays of V shaped intermediate regions which will become transistors. Silicon oxide fills these slots and separates the transistor regions from the substrate. Orthogonal slots divided the semiarrays into individual transistor active regions which are doped by one of N or P doping introduced into each active regions via the orthogonal slots and driven in to comprise the emitter and collector regions on respective sides of original substrate comprising the base regions. Metallization patterns complete electrical connections to the emitter base and collector regions and silicon oxide substantially covers the periphery of each active region for total isolation. Each transistor may further comprise a doped region called P or N doping extending into and across the top of the base region underneath the metallization to reduce space region contact resistance and to provide an electron reflecting potential barrier. Each transistor may further comprise a doped skin of either P or N doping to force electrons toward the center of the base region.
Inventors
- 👤 Sidney I. Soclof
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:41
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10D; H10D10/00; H10D10/60; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D62/184; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0148; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
169 words
A method for producing an array of VLSI dimensioned NPN type lateral transistors formed on a silicon substrate doped P-type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; N+ doping each of said active regions via said second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original P substrate comprising the base regions; further oxidizing said substrate to insure that all slots are filled and insure total peripheral oxide isolation of each transistor active region; and, forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 2
Independent Claim
169 words
A method for producing an array of VLSI dimensioned NPN type lateral transistors formed on a silicon substrate doped P-type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; N+ doping each of said active regions via said second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original P substrate comprising the base regions; further oxidizing said substrate to insure that all slots are filled and insure total peripheral oxide isolation of each transistor active region; and, forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 3
Dependent Claim
40 words
A method in accordance with claim 1, wherein: further P+ doping a region extending into and across the top of the base region underneath the metallization to reduce base region contact resistance and to provide an electron deflecting potential barrier.
Claim 4
Independent Claim
100 words
A method for producing an array of VLSI dimensioned PNP type lateral transistors formed on a silicon substrate doped N-type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions;
Claim 5
Independent Claim
100 words
A method for producing an array of VLSI dimensioned PNP type lateral transistors formed on a silicon substrate doped N-type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; oxidizing the substrate and intermediate regions to fill said slots and cover the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions;
Claim 6
Dependent Claim
69 words
P+ doping each of said active regions via said second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original N substrate comprising the base regions; further oxidizing said substrate to insure that all slots are filled and insure total peripheral oxide isolation of each transistor active region; and, forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 7
Dependent Claim
69 words
P+ doping each of said active regions via said second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original N substrate comprising the base regions; further oxidizing said substrate to insure that all slots are filled and insure total peripheral oxide isolation of each transistor active region; and, forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 8
Dependent Claim
40 words
A method in accordance with claim 3, wherein: further N+ doping a region extending into and across the top of the base region underneath the metallization to reduce base region contact resistance and to provide a hole deflecting potential barrier.
Claim 9
Independent Claim
169 words
A method for producing an array of VLSI dimensioned lateral transistors formed on a silicon substrate doped P or N type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; silicon oxide filling said slots and covering the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; doping of one of N and P each of said active regions via said second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original substrate comprising the base regions; further oxidizing said substrate to insure that all slots are filled and insure total peripheral oxide isolation of each transistor active region; and, forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 10
Independent Claim
169 words
A method for producing an array of VLSI dimensioned lateral transistors formed on a silicon substrate doped P or N type, comprising the steps of: forming a plurality of first sidewalls of pairs of intersecting slots in spaced apart relation across the substrate defining semi-arrays of V shaped intermediate regions which will become transistors; silicon oxide filling said slots and covering the surface of the substrate through which they were made; forming a plurality of second sidewalls of orthogonal slots relative to said pairs of slots dividing the semi-arrays of regions into individual transistor active regions; doping of one of N and P each of said active regions via said second sidewalls; driving in said doping to comprise emitter and collector regions on respective sides of original substrate comprising the base regions; further oxidizing said substrate to insure that all slots are filled and insure total peripheral oxide isolation of each transistor active region; and, forming metallization patterns in electrical connection with the respective emitter, base and collector regions.
Claim 11
Dependent Claim
47 words
A method in accordance with claim 5, wherein: further doping a region of one of P and N extending into and across the top of the base region underneath the metallization to reduce base region contact resistance and to provide an electron or hole deflecting potential barrier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |