Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
174 words
Apparatus for converting a binary representation of a residue signal {m1, m2, m3} in a prescribed residue number system that is defined by the moduli set {p1=2 n -1, p2=2 n , p3=2 n +1}, where n is an integer, to an associated binary output signal r(m1,m2,m3), said apparatus comprising: first means responsive to the residue digit signals m1 and m3 for producing a signal on a plurality of lines that is the sum of the product terms m1*S3 and m3*S1, taken modulo p1*p3, where S1=p1*p2/2 and S3=p2*p3/2; second means for producing an output signal corresponding to the difference between bits of the modulo p1*p2 output signal of said first means and the residue digit signal m2, taken modulo p2; third means for producing an associated binary output signal representative of the product of the output signal of said second means and the constants p1 and p3; and fourth means for combining the output signals of said first and third means for producing the binary output signal r(m1,m2,m3) corresponding to the residue signal {m1,m2,m3}.
Claim 2
Dependent Claim
174 words
Apparatus for converting a binary representation of a residue signal {m1, m2, m3} in a prescribed residue number system that is defined by the moduli set {p1=2 n -1, p2=2 n , p3=2 n +1}, where n is an integer, to an associated binary output signal r(m1,m2,m3), said apparatus comprising: first means responsive to the residue digit signals m1 and m3 for producing a signal on a plurality of lines that is the sum of the product terms m1*S3 and m3*S1, taken modulo p1*p3, where S1=p1*p2/2 and S3=p2*p3/2; second means for producing an output signal corresponding to the difference between bits of the modulo p1*p2 output signal of said first means and the residue digit signal m2, taken modulo p2; third means for producing an associated binary output signal representative of the product of the output signal of said second means and the constants p1 and p3; and fourth means for combining the output signals of said first and third means for producing the binary output signal r(m1,m2,m3) corresponding to the residue signal {m1,m2,m3}.
Claim 3
Dependent Claim
14 words
Apparatus according to claim 1 wherein said fourth means comprises a first adder circuit.
Claim 4
Dependent Claim
15 words
Apparatus according to claim 2 wherein said first adder circuit is a first binary adder.
Claim 5
Dependent Claim
30 words
Apparatus according to claim 3 wherein said second means is responsive to the n less significant bits of the output signal of said first means on associated output lines thereof.
Claim 6
Dependent Claim
41 words
Apparatus according to claim 4 wherein said second means comprises a second adder circuit for producing an output signal corresponding to the difference between bits of the modulo p1*p2 output signal of said first means and the residue digit signal m2.
Claim 7
Dependent Claim
14 words
Apparatus according to claim 5 wherein said second adder circuit is a modulo adder.
Claim 8
Dependent Claim
15 words
Apparatus according to claim 6 wherein said second adder circuit operates modulo 2 n .
Claim 9
Dependent Claim
15 words
Apparatus according to claim 7 wherein said second adder circuit comprises a second binary adder.
Claim 10
Dependent Claim
38 words
Apparatus according to claim 7 wherein said second adder circuit comprises a second binary adder which ignores any overflow caused by a carry generated during operation thereof so as to operate as a modulo 2 n adder circuit.
Claim 11
Dependent Claim
54 words
Apparatus according to claim 8 wherein said third means is a first memory means storing a look-up table with values of the product terms p1, p3 and possible values of the output signal of said second means being stored in associated memory locations which are addressed by the output signal of said second means.
Claim 12
Dependent Claim
81 words
Apparatus according to claim 8 wherein said third means comprises: fifth means inserting 2n binary 0's as the less significant bits ahead of the bits in the output signal of said second means for producing a bit shifted signal; and sixth means operative for producing a prescribed product signal which is the difference between the bit shifted signal and the output signal of said second means, said prescribed product signal being one of the signals operated on by said fourth means.
Claim 13
Dependent Claim
14 words
Apparatus according to claim 11 wherein said sixth means comprises a third binary adder.
Claim 14
Dependent Claim
47 words
Apparatus according to claim 8 wherein said first means comprises a first memory mean containing a look-up table of modulo p1*p3 sums of the possible values of the m1*S3 and m3*S1 product terms in associated memory locations which are addressed by the residue signals m1 and m3.
Claim 15
Dependent Claim
83 words
Apparatus according to claim 8 wherein said first means comprises: first memory means storing a look-up table of product terms m1*S3 in associated memory locations which are addressed by the residue signal m1; second memory means storing a look-up table of possible values of the products m3*S1 in associated memory locations which are addressed by values of the residue digit signal m3; and a second modulo adder for performing modulo p1*p3 addition of selected product terms from said first and second memory means.
Claim 16
Dependent Claim
51 words
Apparatus according to claim 13 wherein said third means comprises second memory means storing a look-up table with values of the product terms p1, p3 and possible values of the output signal of said second means in associated memory locations which are addressed by the output signal of said second means.
Claim 17
Dependent Claim
81 words
Apparatus according to claim 13 wherein said third means comprises: fifth means inserting 2n binary 0's as the less significant bits ahead of the bits in the output signal of said second means for producing a bit shifted signal; and sixth means operative for producing a prescribed product signal which is the difference between the bit shifted signal and the output signal of said second means, said prescribed product signal being one of the signals operated on by said fourth means.
Claim 18
Dependent Claim
14 words
Apparatus according to claim 16 wherein said sixth means comprises a third binary adder.
Claim 19
Dependent Claim
35 words
Apparatus according to claim 17 wherein said second adder circuit comprises a second binary adder which ignores overflow of a carry generated during operation thereof so as to operate as a modulo 2 n adder.
Claim 20
Dependent Claim
32 words
Apparatus according to claim 1 further comprising a digital to analog converter responsive to the output signal of said fourth means for producing an analog signal corresponding to the residue signal {m1,m2,m3}.