US4584528A
Expired / Lapsed
US
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Speed detecting method and apparatus
Assignee: Hitachi Ltd
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Filing: 1982-02-25
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Granted: 1986-04-22
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Expires: 2002-02-25
Abstract
Abstract A counter is provided to count an output pulse which a pulse generator generates each time a vehicle moves by a predetermined distance. A microprocessor is provided to actuate a timer in synchronism with the leading edges of the output pulse from the pulse generator. The timer is set to a constant time interval during which the speed of the vehicle is to be detected. The microprocessor calculates the speed of the vehicle from the count of the counter which count is a value during the time interval from when the timer starts to operate to when the pulse generator generates a pulse just before or after the end point of the set time interval. Thus, the speed of the vehicle can be detected with good resolution and precision.
Inventors
- 👤 Tsutomu Ohmae
- 👤 Toshihiko Matsuda
- 👤 Makoto Tachikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:32
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/481; G01P3/489
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
222 words
A speed detecting apparatus comprising: a pulse generator means for generating a first pulse each time a vehicle moves by a predetermined distance; first counting means for counting the first pulses delivered from said pulse generator means; oscillator means for generating a clock pulse with a constant frequency higher than the frequency of generation of said first pulse; second counting means for counting the clock pulses delivered from said oscillator means; interruption pulse generating means for generating an interruption pulse in synchronism with the generation of said first pulse; timer means for generating a time interruption pulse each time a set time interval has lapsed; and microprocessor means responsive to receipt of said interruption pulse and said time interruption pulse for calculating the speed of said vehicle on the basis of a count value of said first counting means during a time interval from when a pulse is generated by said pulse generator at or adjacent the measuring start point of said set time interval to when a pulse is generated by said pulse generator just before or after the end point of said set time interval and a count value of said second counting means during said time interval, said microprocessor means operating to control said interruption pulse generating means so as to selectively inhibit the generation of said interruption pulse.
Claim 2
Dependent Claim
222 words
A speed detecting apparatus comprising: a pulse generator means for generating a first pulse each time a vehicle moves by a predetermined distance; first counting means for counting the first pulses delivered from said pulse generator means; oscillator means for generating a clock pulse with a constant frequency higher than the frequency of generation of said first pulse; second counting means for counting the clock pulses delivered from said oscillator means; interruption pulse generating means for generating an interruption pulse in synchronism with the generation of said first pulse; timer means for generating a time interruption pulse each time a set time interval has lapsed; and microprocessor means responsive to receipt of said interruption pulse and said time interruption pulse for calculating the speed of said vehicle on the basis of a count value of said first counting means during a time interval from when a pulse is generated by said pulse generator at or adjacent the measuring start point of said set time interval to when a pulse is generated by said pulse generator just before or after the end point of said set time interval and a count value of said second counting means during said time interval, said microprocessor means operating to control said interruption pulse generating means so as to selectively inhibit the generation of said interruption pulse.
Claim 3
Dependent Claim
28 words
A speed detecting apparatus according to claim 1, wherein said timer starts counting said set time interval in response to a pulse generated by said pulse generator means.
Claim 4
Dependent Claim
42 words
A speed detecting apparatus according to claim 1, wherein said microprocessor allows the generation of said interruption pulse only during a time interval from the reception of said time interruption pulse to when said interruption pulse generating means generates an interruption pulse.
Claim 5
Dependent Claim
102 words
A speed detecting apparatus according to claim 1, further comprises reset pulse generating means for generating a reset pulse each time a first pulse is generated from said pulse generator means to thereby reset said second counting means, wherein said microcomputer determines the speed of said vehicle on the basis of a count value of said first counting means and a value obtained by subtracting a count value of said second counting means at a time point where the time interruption pulse is generated from a count value of said second counting means at the end point of said set time interval.
Claim 6
Dependent Claim
31 words
A speed detecting apparatus according to claim 1, wherein said timer makes said set time interval larger when a change of speed of said vehicle is less than a set value.
Claim 7
Dependent Claim
196 words
A speed detecting apparatus comprising: pulse generator means for generating a first pulse each time a vehicle moves by a predetermined distance; first counting means for counting the first pulses delivered from said pulse generator means; oscillator means for generating a clock pulse with a constant frequency higher than the frequency of generation of said first pulse; second counting means for counting the clock pulses delivered from said oscillator means; interruption pulse generating means for generating an interruption pulse in synchronism with the generation of said first pulse; timer means for generating a time interruption pulse each time set time interval has lapsed; and microprocessor means responsive to receipt of said interruption pulse and said time interruption pulse for (a) initiating the start of said timer means, (b) inhibiting operation of said interruption pulse generating means during the period after said timer means has been started and prior to generation of said time interruption pulse, (c) reading the contents of said first and second counting means following the receipt of said time interruption pulse, and (d) calculating the speed of said vehicle on the basis of the read contents of said first and second counting means.
Claim 8
Dependent Claim
196 words
A speed detecting apparatus comprising: pulse generator means for generating a first pulse each time a vehicle moves by a predetermined distance; first counting means for counting the first pulses delivered from said pulse generator means; oscillator means for generating a clock pulse with a constant frequency higher than the frequency of generation of said first pulse; second counting means for counting the clock pulses delivered from said oscillator means; interruption pulse generating means for generating an interruption pulse in synchronism with the generation of said first pulse; timer means for generating a time interruption pulse each time set time interval has lapsed; and microprocessor means responsive to receipt of said interruption pulse and said time interruption pulse for (a) initiating the start of said timer means, (b) inhibiting operation of said interruption pulse generating means during the period after said timer means has been started and prior to generation of said time interruption pulse, (c) reading the contents of said first and second counting means following the receipt of said time interruption pulse, and (d) calculating the speed of said vehicle on the basis of the read contents of said first and second counting means.
Claim 9
Dependent Claim
27 words
A speed detecting apparatus according to claim 6, wherein said microprocessor means initiates the start of said timer means in response to receipt of an interruption pulse.
Claim 10
Dependent Claim
26 words
A speed detecting apparatus according to claim 6, further including means for resetting said second counting means in response to each generation of a first pulse.
Claim 11
Dependent Claim
26 words
A speed detecting apparatus according to claim 8, wherein said first and second counting means are read immediately following the receipt of said time interruption pulse.
Claim 12
Dependent Claim
61 words
A speed detecting apparatus according to claim 6, wherein said microprocessor means is responsive to receipt of said time interruption pulse for removing the inhibition of operation of said interrupt pulse generating means and operates to read the contents of said first and second counting means in response to receipt of an interruption pulse after receipt of said time interruption pulse.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |