Patent US4584055A successfully refreshed from Google Patents.
US4584055A
Expired / Lapsed
US
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Method for manufacturing a semiconductor device
Assignee: Sony Corp
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Filing: 1984-07-19
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Granted: 1986-04-22
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Expires: 2004-07-19
Abstract
Abstract Utilizing the fact that an isotropic etching rate of a semiconductor layer such as a polycrystalline or amorphous silicon layer depends on a doped amount of an impurity doped into the semiconductor layer, the impurity is doped into a semiconductor layer (26) formed on a substrate (4) so as to have a concentration distribution in its thickness direction. Then, in a region of the semiconductor layer (26) to be selectively removed, an anisotropic etching is carried out such that a portion of high impurity concentration is removed and a portion thereof in the thickness direction is remained. Thereafter, the remained portion is subjected to an isotropic etching to thereby suppress the side etching.
Inventors
- 👤 Akio Kayanuma
- 👤 Minoru Nakamura
- 👤 Katsuaki Asano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:29
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D48/345; H10P; H10P54/00; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10P32/00; H10P32/30; H10P32/302; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; H10P50/60; H10P50/64; H10P50/642; H10P50/644; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/924
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
85 words
A method for manufacturing a semiconductor device including an etching process for selectively removing a semiconductor layer formed on a substrate, said method comprising the steps of implanting into said semiconductor layer an impurity with etching-resistant property relative to an isotropic etching of said semiconductor layer, anisotropic-etching away a region of said semiconductor layer to be selectively etched away with its portion in its thickness direction being remained, and removing said remained portion in said thickness direction of said semiconductor layer by the isotropic etching.
Claim 2
Independent Claim
85 words
A method for manufacturing a semiconductor device including an etching process for selectively removing a semiconductor layer formed on a substrate, said method comprising the steps of implanting into said semiconductor layer an impurity with etching-resistant property relative to an isotropic etching of said semiconductor layer, anisotropic-etching away a region of said semiconductor layer to be selectively etched away with its portion in its thickness direction being remained, and removing said remained portion in said thickness direction of said semiconductor layer by the isotropic etching.
Claim 3
Independent Claim
103 words
A method for manufacturing a semiconductor device including an etching process for selectively removing a semiconductor layer formed on a substrate, said method comprising the steps of implanting into said semiconductor layer an impurity with etching-resistant property relative to an isotropic etching of said semiconductor layer, anisotropic etching away a region of said semiconductor layer to be selectively etched away with its portion in its thickness direction, being remained diffusing said impurity into a region of said semiconductor layer which is not etched away by annealing, and removing said remained portion in said thickness direction of said semiconductor layer by the isotropic etching.
Claim 4
Independent Claim
103 words
A method for manufacturing a semiconductor device including an etching process for selectively removing a semiconductor layer formed on a substrate, said method comprising the steps of implanting into said semiconductor layer an impurity with etching-resistant property relative to an isotropic etching of said semiconductor layer, anisotropic etching away a region of said semiconductor layer to be selectively etched away with its portion in its thickness direction, being remained diffusing said impurity into a region of said semiconductor layer which is not etched away by annealing, and removing said remained portion in said thickness direction of said semiconductor layer by the isotropic etching.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-21 | 1989-10-21 | 1990-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-21 | 1993-10-21 | 1994-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-21 | 1997-10-21 | 1998-04-22 | $7700.00 | Window Closed / Lapsed |