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Patent US4583211A successfully refreshed from Google Patents.
US4583211A
Expired / Lapsed
US
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Frequency detecting circuit for digital information reproducing system
Assignee: Toshiba Corp
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Filing: 1983-03-24
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Granted: 1986-04-15
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Expires: 2003-03-24
Abstract
Abstract A circuit is disclosed which is applied for a digital audio disk (DAD) system for detecting a maximum inverting period of a digital audio signal optically read out from the DAD. The audio signal is prestored in the DAD so as to have the maximum and minimum inverting periods specially set by an eight to fourteen modulation (EFM). The detection circuit includes an edge detector for detecting pulse edges of the digital audio signal, a counter for counting pulse edge intervals on the basis of a modulating clock signal, a counter type register, and a comparator. When the register contents of the counter type register is smaller than the count value of the counter, the comparator produces a pulse signal by which said register updates the contents of the register by "1". Repeating this operation, a maximum inverting period value of the digital audio signal is obtained in a fixed period of time.
Inventors
- 👤 Meisei Nishikawa
- 👤 Yukio Nakamura
- 👤 Tadashi Kojima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:36
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/09; G11B27/00; G11B27/10; G11B27/34; G11B19/00; G11B19/20; G11B19/28; G11B20/00; G11B20/10; G11B20/10527; G11B20/14; G11B20/1403; G11B20/1423; G11B20/18; G11B20/1806; G11B7/00; G11B7/004; G11B7/005; G11B2220/00; G11B2220/20
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
206 words
A circuit for detecting one of the maximum and minimum periods of time during which a digital information signal remains in one logic state, said signal being modulated and prestored in a recording medium and said maximum and minimum periods being preset according to the particular modulation system used, said circuit comprising: counter means for: (1) receiving said digital information signal, (2) counting a time duration during which the digital information signal continuously holds its signal level at one logic level, and (3) producing count result data indicative of said time duration; and register means coupled to said counter means, for: (1) storing therein a register value corresponding to a period of time, (2) determining the time difference between said stored register value and said counter result data, (3) selectively changing said register value by a predetermined unit value which is fixed irrespective of the actual degree of said difference between said count result data and said register value, and to said stored register value to form a new register value, and (4) repeating said new register value forming operation to finally produce data equivalent to one of said maxinum; and minimum periods of time during which said digital information signals remains in one logic state.
Claim 2
Dependent Claim
206 words
A circuit for detecting one of the maximum and minimum periods of time during which a digital information signal remains in one logic state, said signal being modulated and prestored in a recording medium and said maximum and minimum periods being preset according to the particular modulation system used, said circuit comprising: counter means for: (1) receiving said digital information signal, (2) counting a time duration during which the digital information signal continuously holds its signal level at one logic level, and (3) producing count result data indicative of said time duration; and register means coupled to said counter means, for: (1) storing therein a register value corresponding to a period of time, (2) determining the time difference between said stored register value and said counter result data, (3) selectively changing said register value by a predetermined unit value which is fixed irrespective of the actual degree of said difference between said count result data and said register value, and to said stored register value to form a new register value, and (4) repeating said new register value forming operation to finally produce data equivalent to one of said maxinum; and minimum periods of time during which said digital information signals remains in one logic state.
Claim 3
Dependent Claim
47 words
The circuit according to claim 1, further comprising comparator means, connected to said counter means and to said register means, for comparing said count data with said register value to generate an output signal, thereby causing said register means to operate in response to said output signal.
Claim 4
Dependent Claim
53 words
The circuit according to claim 2, further comprising detector means connected to said counter means, for receiving said digital information signal to detect level changing points of said digital information signal between a first logic level and a second logic level, and for supplying a detection signal indicative thereof to said counter means.
Claim 5
Dependent Claim
38 words
The circuit according to claim 3, wherein said counter means receives a reference pulse signal and said detection signal to count a time interval between said logic level changing points on the basis of said reference pulse signal.
Claim 6
Dependent Claim
77 words
The circuit according to claim 2, further comprising logic operation element means connected to said counter means, for (1) receiving a reference pulse signal and said digital information signal which alternately assumes first and second logic levels, (2) detecting a time period that a signal level of said information signal is continuously held at one of said first and second logic levels, and (3) supplying a detection signal indicative of said time period to said counter means.
Claim 7
Dependent Claim
81 words
The circuit according to claim 2, wherein said counter means includes a counter circuit of n bit, where n is a positive integer, which divides the count result data of n bits into first count result data corresponding to the upper m bit where m is a positive integer which is less than n, and a second count result data of n-m bit, and separately produces first and second data, said second counter result data being supplied to said comparator means.
Claim 8
Dependent Claim
98 words
The circuit according to claim 6, further comprising AND gate means, having a first input connected to said counter means, a second input connected to said comparator means, and an output connected to said register means, for receiving said first count result data and said output signal at said first input and said second inputs thereof respectively, to produce a logically sum of said first count result data and said output signal, whereby the number of bits of said register means is reduced to lhe n-m number of bits of second count results data from said counter means.
Claim 9
Dependent Claim
129 words
The circuit according to claim 3, wherein said counter means comprises: a first counter which receives a reference pulse signal and said detection signal and counts a time interval between said logic level changing points on the basis of said reference pulse signal; an inverter for receiving said reference pulse signal to logically invert said reference pulse signal; a second counter arranged in parallel with said first counter and connected to said inverter, which receives a reference pulse signal inverted by said inverter and said detection signal, and counts a time interval between said logic level changing points on the basis of said inverted reference pulse signals; and adding means connected to said first and second counters, for receiving and adding output data from said first and second counters.
Claim 10
Dependent Claim
130 words
The circuit according to claim 3, wherein said counter means comprises: a frequency divider for receiving and frequency-dividing a reference pulse signal into a signal with a frequency of 1/N is a positive integer; N-stage shift registers connected to said frequency divider, which receives said reference pulse signal with the 1/N frequency, and which sequentially shifts said reference pulse signal to product N clock pulse signals; counters of N arranged in parallel to each other, which receive said detection signal from said detector means and receive said N clock pulse signals, respectively, to count time intervals between logic level changing points on the basis of said N clock pulse signals, respectively; and adding means connected to said counters, for receiving and adding the output data from said counters of N.
Claim 11
Dependent Claim
21 words
A circuit as in claim 1 further comprising a digital audio disk system wherein said circuit is used within said system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |