Patent US4583203A successfully refreshed from Google Patents.
US4583203A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory output circuit
Assignee: STC PLC
•
Filing: 1983-12-08
•
Granted: 1986-04-15
•
Expires: 2003-12-08
Abstract
Abstract An energy efficient output circuit for a static random access memory includes a pair of output transistors each driven by a bootstrapped driver stage. This requires less current than conventional amplifier chain.
Inventors
- 👤 Trevor K. Monk
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:03
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01714; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/106; H03K5/00; H03K5/01; H03K5/02; H03K5/023; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
113 words
In a semiconductor memory, an output circuit comprising: an output transistor series pair, each transistor of said pair being coupled to a respective bootstrapped driver circuit; driver means for driving said bootstrapped driver circuits with signals of a voltage level less than the operating voltage of the memory and corresponding to memory output data; and said driver means including a first preamplifier serving as a sense amplifier, a second preamplifier connected to the output of said first preamplifier and provided with positive capacitive feedback, and a logic level converter having an output pair of source follower transistors provided with cross-coupled load transistors, the sources of the load transistors being connected to circuit ground.
Claim 2
Dependent Claim
113 words
In a semiconductor memory, an output circuit comprising: an output transistor series pair, each transistor of said pair being coupled to a respective bootstrapped driver circuit; driver means for driving said bootstrapped driver circuits with signals of a voltage level less than the operating voltage of the memory and corresponding to memory output data; and said driver means including a first preamplifier serving as a sense amplifier, a second preamplifier connected to the output of said first preamplifier and provided with positive capacitive feedback, and a logic level converter having an output pair of source follower transistors provided with cross-coupled load transistors, the sources of the load transistors being connected to circuit ground.
Claim 3
Dependent Claim
23 words
A circuit in accordance with claim 1, wherein each of said load transistors comprises a plurality of parallel-connected transistors having different threshold voltages.
Claim 4
Dependent Claim
22 words
A circuit in accordance with claim 1, wherein said first preamplifier, said second preamplifier and said logic level converter comprise balanced stages.
Claim 5
Dependent Claim
119 words
In a semiconductor memory, an output circuit fabricated by an NMOS process and comprising: an output transistor series pair, each transistor of said pair being coupled to a respective bootstrapped driver circuit; driver means for driving said bootstrapped drive circuits with signals of a voltage level less than the operating voltage of the memory and corresponding to memory output data; and said driver means including a first preamplifier serving as a sense amplifier, a second preamplifier connected to the output of said first preamplifier and provided with positive capacitive feedback, and a logic level connecter having an output pair of source follow transistors provided with cross-coupled load transistors, the sources of the load transistors being connected to circuit ground.
Claim 6
Dependent Claim
119 words
In a semiconductor memory, an output circuit fabricated by an NMOS process and comprising: an output transistor series pair, each transistor of said pair being coupled to a respective bootstrapped driver circuit; driver means for driving said bootstrapped drive circuits with signals of a voltage level less than the operating voltage of the memory and corresponding to memory output data; and said driver means including a first preamplifier serving as a sense amplifier, a second preamplifier connected to the output of said first preamplifier and provided with positive capacitive feedback, and a logic level connecter having an output pair of source follow transistors provided with cross-coupled load transistors, the sources of the load transistors being connected to circuit ground.
References Cited (Backward Citations)
GB1520078A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |