US4583192A
Expired / Lapsed
US
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MOS full adder circuit
Assignee: Motorola Solutions Inc
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Filing: 1983-09-30
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Granted: 1986-04-15
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Expires: 2003-09-30
Abstract
Abstract An MOS full adder circuit having a sum circuit portion and a carry circuit portion is provided. In an embodiment utilizing transistors of opposite conductivity type, both the sum and carry circuits are symmetrical, thereby simplifying the physical layout of the full adder during fabrication.
Inventors
- 👤 Ronald H. Cieslak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:49
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
452 words
In an MOS full adder circuit, an output carry bit circuit for providing an output carry bit resulting from the addition of a first and a second input add bit in association with a predetermined input carry bit, said output carry bit circuit comprising: a first transistor of a first conductivity type having a first current electrode connected to a power supply terminal, a control electrode for receiving the input carry bit, and a second current electrode connected to a first node; a second transistor of the first conductivity type having a first current electrode connected to the first node, a control electrode for receiving the first input add bit, and a second current electrode connected to an output terminal for providing the output carry bit; a third transistor of the first conductivity type having a first current electrode connected to the power supply terminal, a control electrode for receiving the first input add bit, and a second current electrode connected to a second node; a fourth transistor of the first conductivity type having a first current electrode connected to the second node, a control electrode for receiving the second add bit, and a second current electrode connected to the output terminal; a first bridge transistor of the first conductivity type having a first current electrode connected to the first node, a control electrode for receiving the second input add bit, and a second current electrode connected to the second node, for selectively bridging the first node to the second node; a fifth transistor of a second conductivity type having a first current electrode connected to the output terminal, a control electrode for receiving the first input add bit, and a second current electrode connected to a third node; a sixth transistor of the second conductivity type having a first current electrode connected to the third node, a control electrode for receiving the input carry bit, and a second current electrode connected to a reference terminal; a seventh transistor of the second conductivity type having a first current electrode connected to the output terminal, a control electrode for receiving the second input add bit, and a second current electrode connected to a fouth node; an eighth transistor of the second conductivity type having a first current electrode connected to the fourth node, a control electrode for receiving the first input add bit, and a second current electrode connected to the reference terminal; and a second bridge transistor of the second conductivity type having a first current electrode connected to the third node, a control electrol for receiving the second input add bit, and a second current electrode connected to the fourth node, for selectively bridging the third node to the fourth node.
Claim 2
Dependent Claim
452 words
In an MOS full adder circuit, an output carry bit circuit for providing an output carry bit resulting from the addition of a first and a second input add bit in association with a predetermined input carry bit, said output carry bit circuit comprising: a first transistor of a first conductivity type having a first current electrode connected to a power supply terminal, a control electrode for receiving the input carry bit, and a second current electrode connected to a first node; a second transistor of the first conductivity type having a first current electrode connected to the first node, a control electrode for receiving the first input add bit, and a second current electrode connected to an output terminal for providing the output carry bit; a third transistor of the first conductivity type having a first current electrode connected to the power supply terminal, a control electrode for receiving the first input add bit, and a second current electrode connected to a second node; a fourth transistor of the first conductivity type having a first current electrode connected to the second node, a control electrode for receiving the second add bit, and a second current electrode connected to the output terminal; a first bridge transistor of the first conductivity type having a first current electrode connected to the first node, a control electrode for receiving the second input add bit, and a second current electrode connected to the second node, for selectively bridging the first node to the second node; a fifth transistor of a second conductivity type having a first current electrode connected to the output terminal, a control electrode for receiving the first input add bit, and a second current electrode connected to a third node; a sixth transistor of the second conductivity type having a first current electrode connected to the third node, a control electrode for receiving the input carry bit, and a second current electrode connected to a reference terminal; a seventh transistor of the second conductivity type having a first current electrode connected to the output terminal, a control electrode for receiving the second input add bit, and a second current electrode connected to a fouth node; an eighth transistor of the second conductivity type having a first current electrode connected to the fourth node, a control electrode for receiving the first input add bit, and a second current electrode connected to the reference terminal; and a second bridge transistor of the second conductivity type having a first current electrode connected to the third node, a control electrol for receiving the second input add bit, and a second current electrode connected to the fourth node, for selectively bridging the third node to the fourth node.
Claim 3
Dependent Claim
456 words
In an MOS full adder circuit, a sum bit circuit for providing a sum bit resulting from the addition of a first and a second input add bit in association with a predetermined input carry bit, said sum bit circuit comprising: a first transistor of a first conductivity type having a first current electrode connected to a power supply terminal, a control electrode for receiving an input carry bit, and a second current electrode connected to a first node; a second transistor of the first conductivity type having a first current electrode connected to the first node, a control electrode for receiving an output carry bit associated with the addition of the first and second input add bits, and a second current electrode connected to an output terminal for providing the sum bit; a third transistor of the first conductivity type having a first current electrode connected to the power supply terminal, a control electrode for receiving the output carry bit, and a second current electrode connected to a second node; a fourth transistor of the first conductivity type having a first current electrode connected to the second node, a control electrode for receiving the second add bit, and a second current electrode connected to the output terminal; a first bridge transistor of the first conductivity type having a first current electrode connected to the first node, a control electrode for receiving the first input add bit, and a second current electrode connected to the second node, for selectively bridging the first node to the second node; a fifth transistor of a second conductivity type having a first current electrode connected to the output terminal, a control electrode for receiving the second input add bit, and a second current electrode connected to a third node; a sixth transistor of the second conductivity type having a first current electrode connected to the third node, a control electrode for receiving the output carry bit, and a second current electrode connected to a reference terminal; a seventh transistor of the second conductivity type having a first current electrode connected to the output terminal, a control electrode for receiving the output carry bit, and a second current electrode connected to a fourth node; an eighth transistor of the second conductivity type having a first current electrode connected to the fourth node, a control electrode for receiving the input carry bit, and a second current electrode connected to the reference terminal; and a second bridge transistor of the second conductivity type having a first current electrode connected to the third node, a control electrol for receiving the first input add bit, and a second current electrode connected to the fourth node, for selectively bridging the third node to the fourth node.
Claim 4
Dependent Claim
456 words
In an MOS full adder circuit, a sum bit circuit for providing a sum bit resulting from the addition of a first and a second input add bit in association with a predetermined input carry bit, said sum bit circuit comprising: a first transistor of a first conductivity type having a first current electrode connected to a power supply terminal, a control electrode for receiving an input carry bit, and a second current electrode connected to a first node; a second transistor of the first conductivity type having a first current electrode connected to the first node, a control electrode for receiving an output carry bit associated with the addition of the first and second input add bits, and a second current electrode connected to an output terminal for providing the sum bit; a third transistor of the first conductivity type having a first current electrode connected to the power supply terminal, a control electrode for receiving the output carry bit, and a second current electrode connected to a second node; a fourth transistor of the first conductivity type having a first current electrode connected to the second node, a control electrode for receiving the second add bit, and a second current electrode connected to the output terminal; a first bridge transistor of the first conductivity type having a first current electrode connected to the first node, a control electrode for receiving the first input add bit, and a second current electrode connected to the second node, for selectively bridging the first node to the second node; a fifth transistor of a second conductivity type having a first current electrode connected to the output terminal, a control electrode for receiving the second input add bit, and a second current electrode connected to a third node; a sixth transistor of the second conductivity type having a first current electrode connected to the third node, a control electrode for receiving the output carry bit, and a second current electrode connected to a reference terminal; a seventh transistor of the second conductivity type having a first current electrode connected to the output terminal, a control electrode for receiving the output carry bit, and a second current electrode connected to a fourth node; an eighth transistor of the second conductivity type having a first current electrode connected to the fourth node, a control electrode for receiving the input carry bit, and a second current electrode connected to the reference terminal; and a second bridge transistor of the second conductivity type having a first current electrode connected to the third node, a control electrol for receiving the first input add bit, and a second current electrode connected to the fourth node, for selectively bridging the third node to the fourth node.
Claim 5
Dependent Claim
238 words
In an MOS full adder circuit having transistors of a single conductivity type, an output carry bit circuit for providing an output carry bit resulting from the addition of a first and a second input add bit in association with a predetermined input carry bit, said output carry bit circuit comprising: load means connected between a supply voltage terminal for receiving a supply voltage and an output terminal for providing the output carry bit; a first transistor having a first current electrode connected to the output terminal, a control electrode for receiving the first input add bit, and a second current electrode; a second transistor having a first current electrode connected to the output terminal, a control electrode for receiving the second input add bit, and a second current electrode; a third transistor having a first current electrode connected to both of the second current electrodes of the first and second transistors, a control electrode for receiving the input carry bit, and a second current electrode connected to a reference node; a fourth transistor having a first current electrode connected to the output terminal, a control electrode for receiving the first input add bit, and a second current electrode; and a fifth transistor having a first current electrode connected to the second current electrode of the fourth transistor, a control electrode for receiving the second input add bit, and a second current electrode connected to the reference node.
Claim 6
Dependent Claim
238 words
In an MOS full adder circuit having transistors of a single conductivity type, an output carry bit circuit for providing an output carry bit resulting from the addition of a first and a second input add bit in association with a predetermined input carry bit, said output carry bit circuit comprising: load means connected between a supply voltage terminal for receiving a supply voltage and an output terminal for providing the output carry bit; a first transistor having a first current electrode connected to the output terminal, a control electrode for receiving the first input add bit, and a second current electrode; a second transistor having a first current electrode connected to the output terminal, a control electrode for receiving the second input add bit, and a second current electrode; a third transistor having a first current electrode connected to both of the second current electrodes of the first and second transistors, a control electrode for receiving the input carry bit, and a second current electrode connected to a reference node; a fourth transistor having a first current electrode connected to the output terminal, a control electrode for receiving the first input add bit, and a second current electrode; and a fifth transistor having a first current electrode connected to the second current electrode of the fourth transistor, a control electrode for receiving the second input add bit, and a second current electrode connected to the reference node.
Claim 7
Dependent Claim
55 words
The MOS full adder circuit of claim 3, wherein said load means of the output carry bit circuit further comprises: a sixth transistor having a first current electrode connected to a supply voltage terminal for receiving a supply voltage, and both a control electrode and a second current electrode connected together to the output terminal.
Claim 8
Dependent Claim
27 words
The MOS full adder circuit of claim 4, wherein said sixth transistor of the load means of the output carry bit circuit is a depletion type transistor.
Claim 9
Dependent Claim
246 words
In an MOS full adder circuit having transistors of a single conductivity type, a sum bit circuit for providing a sum bit resulting from the addition of a first and a second input add bit in association with a predetermined input carry bit, said sum bit circuit comprising: load means connected between a supply voltage terminal and an output terminal for providing the sum bit; a first transistor having a first current electrode connected to the output terminal, a control electrode for receiving an output carry bit associated with the addition of the first and second add bits, and a second current electrode connected to a first node; a second transistor having a first current electrode connected to the first node, a control electrode connected to the first input add bit, and a second current electrode connected to a reference node; a third transistor having a first current electrode connected to the output terminal, a control electrode for receiving the input carry bit, and a second current electrode connected to a second node; a fourth transistor having a first current electrode connected to the second node, a control electrode for receiving the output carry bit, and a second current electrode connected to the reference node; and a bridge transistor for selectively coupling the first and second nodes having a first current electrode connected to the first node, a second current electrode connected to the second node, and a control electrode for receiving the second input bit.
Claim 10
Dependent Claim
246 words
In an MOS full adder circuit having transistors of a single conductivity type, a sum bit circuit for providing a sum bit resulting from the addition of a first and a second input add bit in association with a predetermined input carry bit, said sum bit circuit comprising: load means connected between a supply voltage terminal and an output terminal for providing the sum bit; a first transistor having a first current electrode connected to the output terminal, a control electrode for receiving an output carry bit associated with the addition of the first and second add bits, and a second current electrode connected to a first node; a second transistor having a first current electrode connected to the first node, a control electrode connected to the first input add bit, and a second current electrode connected to a reference node; a third transistor having a first current electrode connected to the output terminal, a control electrode for receiving the input carry bit, and a second current electrode connected to a second node; a fourth transistor having a first current electrode connected to the second node, a control electrode for receiving the output carry bit, and a second current electrode connected to the reference node; and a bridge transistor for selectively coupling the first and second nodes having a first current electrode connected to the first node, a second current electrode connected to the second node, and a control electrode for receiving the second input bit.
Claim 11
Dependent Claim
54 words
The MOS full adder circuit of claim 6 wherein said load means of the sum bit circuit further comprise: a fifth transistor having a first current electrode connected to a supply voltage terminal for receiving a supply voltage, and both a control electrode and a second current electrode connected together to the output terminal.
Claim 12
Dependent Claim
22 words
The MOS full adder circuit of claim 7 wherein said fifth transistor of the sum bit circuit is a depletion type transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |