Look ahead memory interface

Claim 1

A data processing system for processing a plurality of operands according to a plurality of instructions comprising: a data bus; an address bus; a central processing unit, having a data port connected to said data bus, an address port connected to said address bus, and control outputs, where said central processing unit supplies a series of addresses through said address bus, any given one of said series being the present address and the following sequential one being the next address; at least two addressable instruction memory modules, each having a plurality of addressable locations designated by a plurality of address, an address input, and a data port means for receiving and transmitting said intructions, said data port means being connected to said data bus; at least two address look ahead means for generating a predicted address from said present address, each having an address input connected to said address bus, an address output connected to said address input of an individual one of said addressable memory modules, and control inputs connected to said control outputs of said central processing unit; and an addressable operand memory module for storing said operands, having a plurality of addressable locations designated by a plurality of addresses, an address input, and a data port means for receiving and transmitting said operands, said data port means being connected to said data bus and said data port means having control inputs connected to said control outputs of said central processing unit, and said address input being connected to said address bus, wherein said instructions are numbered and wherein one of said addressable instruction memory modules contains odd-numbered instructions and another of said addressable instruction memory modules contains even-numbered instructions; and wherein said address look ahead means further comprises: incrementing means for incrementing a present address to create a predicted address; storage means for storing said predicted address; address comparison means for comparing said next address with said predicted address, said comparison means having a binary output means, outputting a logical 1 when said predicted and next addresses are identical and a logical 0 when said predicted and next addresses are not identical; switch means for selecting said predicted address when said output of said comparison means is logical 1 and selecting said next address when output of said comparison means is logical 0; flip-flop means having a control input connected to said binary output means of said address comparison means and an output connected to said switch means and said data port means of the respective one of said addressable instruction memory modules; and activator means connected to said control outputs of said central processing unit for activating said address look ahead means; and wherein a portion of said address is designated as the virtual address and wherein said address look ahead means further comprises lookup memory means for generating a real address portion from said virtual address portion, said lookup memory means having an address input connected to said switch means, a data input connected to said data bus, and a data output connected to said address output of said address look ahead means.