Backporch gating pulse generator subject to disabling during vertical sync interval

Claim 2

In a television receiver for receiving composite video signals inclusive of respective line and field deflection synchronizing components, said field deflection synchronizing components occupying periodically recurring vertical sync intervals; a line-rate gating pulse generator, subject to field-rate disabling, for developing gating pulses, comprising: a source of periodic timing pulses recurring at a line rate; a source of field-rate pulses indicative of the timing of said recurring vertical sync intervals; an output load across which said generator develops said gating pulses; a DC potential supply; first and second transistors having normally conducting emitter-collector paths, the emitter-collector path of said first transistor being serially coupled with said output load across said DC potential supply; a first resistor, a capacitor, and a second resistor connected in series across said DC potential supply; the emitter-collector path of said second transistor being shunted across the series combination of said capacitor and said second resistor; means for utilizing said timing pulses to suppress conduction in the emitter-collector paths of said first and second transistors during each timing pulse appearance; a third transistor, responsive to said field-rate pulses, and having an emitter-collector path rendered non-conductive during each field-rate pulse appearance but maintained in a conductive state during the periods intervening between successive field-rate pulse appearances; a diode, the series combination of said diode and the emitter-collector path of said third transistor being connected in shunt with said second resistor, with said diode being poled so as to exhibit a conducting state when suppression of conduction in the emitter-collector path of said second transistor coincides with existence of a conductive state for the emitter-collector path of said third transistor; a fourth transistor having an emitter-collector path connected in shunt with the emitter-collector path of said first transistor; and means for rendering the emitter-collector path of said fourth transistor conducting when the voltage across said series combination of said capacitor and said second resistor exceeds a reference level.

Claim 3

Apparatus in accordance with claim 1, wherein during each field-rate pulse appearance, each initiation of a cutoff of said second transistor is accompanied by a step rise of the voltage across said series combination of said capacitor and said second resistor; the resistance value of said second resistor being such as to ensure that the magnitude of said step rise exceeds the magnitude of said reference level.

Claim 4

Apparatus in accordance with claim 2 wherein the charging time constant of a charging circuit formed by the series combination of said first resistor, said capacitor, said diode in its conductive state, and the emitter-collector path of said third transistor in its conductive state is determinative of the width of the gating pulses appearing during said intervening periods.

Claim 5

Apparatus in accordance with claim 3 wherein said source of timing pulses is responsive to said line deflection synchronization component of said composite video signals.

Claim 6

Apparatus in accordance with claim 4 wherein said field-rate pulses comprise vertical drive pulses generated in response to said field deflection synchronization component of said composite video signals.

Claim 7

In a television receiver, a line-rate gating pulse generator subject to periodic field-rate disabling comprising: a source of periodic line-rate timing pulses; a source of periodic field-rate pulses; a source of DC potential; and means, responsive to said timing pulses, for developing gating pulses with leading edges normally determined by the leading edges of said timing pulses; wherein said gating pulse developing means includes: means for controlling the width of said gating pulses, said width controlling means normally operating in a first mode establishing a substantially fixed, finite width for said gating pulses; and means, responsive to said field rate pulses, for altering the mode of operation of said width controlling means during each field-rate pulse occurrence to a second mode in which the width of said gating pulses is reduced to zero so as to effect a desired field-rate suppression of said gating pulses; wherein said width controlling means includes a first resistor, a capacitor and a second resistor serially connected across said DC potential source, said second resistor being shunted by a low impedance current path during operations in said first mode; and wherein said mode altering means comprises means for disabling said current path during each field-rate pulse occurrence.

Claim 8

In a television receiver, a line-rate gating pulse generator subject to periodic field-rate disabling comprising: a source of periodic line-rate timing pulses; a source of periodic field-rate pulses; a source of DC potential; and means, responsive to said timing pulses, for developing gating pulses with leading edges normally determined by the leading edges of said timing pulses; wherein said gating pulse developing means includes: means for controlling the width of said gating pulses, said width controlling means normally operating in a first mode establishing a substantially fixed, finite width for said gating pulses; and means, responsive to said field rate pulses, for altering the mode of operation of said width controlling means during each field-rate pulse occurrence to a second mode in which the width of said gating pulses is reduced to zero so as to effect a desired field-rate suppression of said gating pulses; wherein said width controlling means includes a first resistor, a capacitor and a second resistor serially connected across said DC potential source, said second resistor being shunted by a low impedance current path during operations in said first mode; and wherein said mode altering means comprises means for disabling said current path during each field-rate pulse occurrence.

Claim 9

In a television receiver, a line-rate gating pulse generator subject to periodic field-rate disabling comprising: a source of periodic line-rate timing pulses; a source of periodic field-rate pulses; a source of DC potential; and means, responsive to said timing pulses, for developing gating pulses with leading edges normally determined by the leading edges of said timing pulses; wherein said gating pulse developing means includes a gating pulse width control circuit subject to keying by said field-rate pulses and inclusive of a first resistor, a capacitor, and a second resistor serially connected across said DC potential source; said gating pulse width control circuit operating in a first mode during periods intervening between successive field-rate appearances, in which first mode said second resistor is effectively bypassed and the RC time constant of said first resistor and said capacitor is determinative of a substantially fixed, finite width for said gating pulses; and said gating pulse width control circuit operating in a second mode during appearances of said field-rate pulses, in which second mode said second resistor is unbypassed and the width of said gating pulses is reduced to zero so as to effect a desired field-rate suppression of gating pulse appearances; said width control circuit also including a diode connected to the junction of said capacitor and said second resistor; wherein said gating pulse developing means also includes: an output load across which said gating pulses are developed; first and second transistors having normally conducting emitter-collector paths, the emitter-collector path of said first transistor being serially coupled with said output load across said DC potential source, and the emitter-collector path of said second transistor being connected in shunt with the series combination of said capacitor and said second resistor; means for rendering the emitter-collector paths of said first and second transistors non-conductive during each timing pulse appearance; an additional transistor having a normally non-conductive emitter-collector path connected in shunt with the emitter-collector path of said first transistor; and means for rendering the emitter-collector path of said additional transistor conducting when the voltage across said series combination of said capacitor and said second resistor exceeds a reference level; and wherein the keying of said gating pulse width control circuit is effected via said diode.

Claim 10

In a television receiver, a line-rate gating pulse generator subject to periodic field-rate disabling comprising: a source of periodic line-rate timing pulses; a source of periodic field-rate pulses; a source of DC potential; and means, responsive to said timing pulses, for developing gating pulses with leading edges normally determined by the leading edges of said timing pulses; wherein said gating pulse developing means includes a gating pulse width control circuit subject to keying by said field-rate pulses and inclusive of a first resistor, a capacitor, and a second resistor serially connected across said DC potential source; said gating pulse width control circuit operating in a first mode during periods intervening between successive field-rate appearances, in which first mode said second resistor is effectively bypassed and the RC time constant of said first resistor and said capacitor is determinative of a substantially fixed, finite width for said gating pulses; and said gating pulse width control circuit operating in a second mode during appearances of said field-rate pulses, in which second mode said second resistor is unbypassed and the width of said gating pulses is reduced to zero so as to effect a desired field-rate suppression of gating pulse appearances; said width control circuit also including a diode connected to the junction of said capacitor and said second resistor; wherein said gating pulse developing means also includes: an output load across which said gating pulses are developed; first and second transistors having normally conducting emitter-collector paths, the emitter-collector path of said first transistor being serially coupled with said output load across said DC potential source, and the emitter-collector path of said second transistor being connected in shunt with the series combination of said capacitor and said second resistor; means for rendering the emitter-collector paths of said first and second transistors non-conductive during each timing pulse appearance; an additional transistor having a normally non-conductive emitter-collector path connected in shunt with the emitter-collector path of said first transistor; and means for rendering the emitter-collector path of said additional transistor conducting when the voltage across said series combination of said capacitor and said second resistor exceeds a reference level; and wherein the keying of said gating pulse width control circuit is effected via said diode.

Claim 11

Apparatus in accordance with claim 7 wherein said source of field-rate pulses includes a further transistor having an emitter-collector path which is non-conductive during said field-rate pulse appearances; the series combination of the emitter-collector path of said further transistor and said diode being connected in shunt with said second resistor.