Patent US4583007A successfully refreshed from Google Patents.
US4583007A
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Failsafe decision circuit
Assignee: Nokia Bell Labs
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Filing: 1985-09-13
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Granted: 1986-04-15
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Expires: 2005-09-13
Abstract
Abstract A decision circuit is responsive to digital input signals and to timing signals for reshaping and retiming the input signals into reshaped and retimed output signals. The decision circuit also is responsive to the digital input signals and absence of the timing signals for reshaping but not retiming the digital input signals into reshaped output signals which are transmitted. Thus the circuit produces and transmits reshaped output signals even upon failure to apply the timing signals required by a prior art decision circuit.
Inventors
- 👤 Robert M. Paski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:10
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K5/00; H03K5/01; H03K5/12; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/20; H04L25/24; H04L25/242
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
88 words
A decision circuit for reshaping data signals in the presence and absence of timing signals comprising clock means responsive to said timing signals for generating periodic clock signals, and processing means responsive to said data signals and said periodic clock signals for generating reshaped and retimed data signals, characterized in that: said clock means includes means responsive to the absence of said timing signals for generating an output current, and means for coupling said output current to said processing means whereby said processing means generates reshaped data signals.
Claim 2
Dependent Claim
88 words
A decision circuit for reshaping data signals in the presence and absence of timing signals comprising clock means responsive to said timing signals for generating periodic clock signals, and processing means responsive to said data signals and said periodic clock signals for generating reshaped and retimed data signals, characterized in that: said clock means includes means responsive to the absence of said timing signals for generating an output current, and means for coupling said output current to said processing means whereby said processing means generates reshaped data signals.
Claim 3
Dependent Claim
29 words
A decision circuit, in accordance with claim 1, wherein said clock means further includes means responsive to said timing signals for producing a quantized timing signal and its complement.
Claim 4
Dependent Claim
82 words
A decision circuit, in accordance with claim 2, wherein said means for generating an output current includes means responsive to said quantized timing signal and its complement for producing a product signal; means responsive to said product signal for developing a substantially constant voltage of one value when said timing signals are present and of a second value when said timing signals are absent; and comparator means responsive to said substantially constant voltage of said second value for generating said output current.
Claim 5
Dependent Claim
24 words
A decision circuit, in accordance with claim 1, wherein the decision circuit is fabricated with opposite conductivity type transistors as a monolithic integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-14 | 1989-10-14 | 1990-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-14 | 1993-10-14 | 1994-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-14 | 1997-10-14 | 1998-04-15 | $7700.00 | Window Closed / Lapsed |