Dynamic random access memory having small cycle time period

Claim 2

A dynamic random access memory having an internal circuit and connected to receive an external control signal comprising: address buffer means; address decoder means having NOR gate means connected to said address buffer means and driver means connected to the internal circuit; active means for applying address signals, via said address buffer means to said address decoder means, so as to perform a memory access operation upon the internal circuit when said active means receives the external control signal, said active means defining an active time period; first reset means for resetting said address buffer means and said NOR gate means of said address decoder means within a predetermined time period shorter than the active time period defined by said active means; and second reset means for resetting said driver means of said address decoder means in response to the external control signal.

Claim 3

A memory as set forth in claim 1, wherein said address decoder means comprises means, connected between said NOR gate means and said driver means, for electrically separating said NOR gate means from said driver means at least during a time period between the time said first reset means performs its resetting operation and the time said second reset means performs its resetting operation.

Claim 4

A memory as set forth in claim 1 wherein: said active means generates first and second control signals; said address buffer means comprises row address buffers controlled by the first control signal and column address buffers controlled by the second control signal.

Claim 5

A memory as set forth in claim 2, further comprising first and second power supply terminals, wherein: said active means generates first, second, third, fourth and fifth control signals; said NOR gate means comprises: a first transistor having a drain connected to said first power supply terminal, having a gate controlled by the first control signal of said active means, and having a source; and a plurality of second transistors connected in parallel, each having a drain connected to the source of said first transistor, having a gate controlled by a corresponding one of the address signals, and having a source connected to said second power supply terminal; said driver means comprises: a third transistor having a drain controlled by the second control signal of said active means, having a gate, and having a source; fourth and fifth transistors crosscoupled with each other, said fourth transistor being connected between said third transistor and said second power supply terminal, said fifth transistor being connected to said second power supply terminal and the internal circuit; and a sixth transistor having a drain connected to the first power supply terminal, having a gate controlled by the third control signal of said active means, and having a source connected to the fifth transistor; said electrical separating means comprises: a seventh transistor having a drain connected to the source of said first transistor, having a gate controlled by the fourth control signal of said active means, and having a source connected to the gate of said third transistor; and an eighth transistor having a drain connected to the gate of said third transistor, having a gate controlled by the fifth control signal of said active means, and having a source connected to the source of said third transistor.

Claim 6

A dynamic random access memory including a memory cell array and connected to receive a first external control signal defining an active time period and a second external control signal, comprising: control means, connected to receive the first and second external control signals, for generating first and second enable signals and first, second, third and fourth reset signals in dependence upon the first and second external control signals; address buffer means, connected to said control means, for receiving the first and second enable signals and for providing first and second address signals; a first decoder circuit, connected to said control means, said address buffer means and the memory cell array, for accessing the memory cell array based on the first address signals and the first enable signal, said first decoder circuit including: a first NOR gate circuit, connected to said control means, for receiving the first enable signal; a first separation circuit, connected to said first NOR gate circuit and said control means, for receiving the first reset signal; and a first driver circuit, connected to said first separation circuit and the memory cell array, for receiving the second reset signal, said first NOR gate circuit being reset in dependence upon the first reset signal within a predetermined time period during the active time period defined by the first external control signal, said first driver circuit being reset in response to the second reset signal; a second decoder circuit, connected to said control means, said address buffer means and the memory cell array, for accessing the memory cell array based on the second address signals and the second enable signal, said second decoder circuit including: a second NOR gate circuit, connected to said control means, for receiving the second enable signal; a second separation circuit, connected to said second NOR gate circuit and said control means, for receiving the third reset signal; and a second driver circuit, connected to said second separation circuit and the memory cell array, for receiving the fourth reset signal, said second NOR gate circuit being reset in dependence upon the third reset signal within a predetermined time period during the active time period defined by the first external control signal, said second driver circuit being reset in response to the fourth reset signal.

Claim 7

A dynamic random access memory including a memory cell array and connected to receive a first external control signal defining an active time period and a second external control signal, comprising: control means, connected to receive the first and second external control signals, for generating first and second enable signals and first, second, third and fourth reset signals in dependence upon the first and second external control signals; address buffer means, connected to said control means, for receiving the first and second enable signals and for providing first and second address signals; a first decoder circuit, connected to said control means, said address buffer means and the memory cell array, for accessing the memory cell array based on the first address signals and the first enable signal, said first decoder circuit including: a first NOR gate circuit, connected to said control means, for receiving the first enable signal; a first separation circuit, connected to said first NOR gate circuit and said control means, for receiving the first reset signal; and a first driver circuit, connected to said first separation circuit and the memory cell array, for receiving the second reset signal, said first NOR gate circuit being reset in dependence upon the first reset signal within a predetermined time period during the active time period defined by the first external control signal, said first driver circuit being reset in response to the second reset signal; a second decoder circuit, connected to said control means, said address buffer means and the memory cell array, for accessing the memory cell array based on the second address signals and the second enable signal, said second decoder circuit including: a second NOR gate circuit, connected to said control means, for receiving the second enable signal; a second separation circuit, connected to said second NOR gate circuit and said control means, for receiving the third reset signal; and a second driver circuit, connected to said second separation circuit and the memory cell array, for receiving the fourth reset signal, said second NOR gate circuit being reset in dependence upon the third reset signal within a predetermined time period during the active time period defined by the first external control signal, said second driver circuit being reset in response to the fourth reset signal.