Patent US4581650A successfully refreshed from Google Patents.
US4581650A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Solid state image sensor arrangement
Assignee: Fujifilm Corp
•
Filing: 1984-04-06
•
Granted: 1986-04-08
•
Expires: 2004-04-06
Abstract
Abstract A solid state image sensor system includes an array of image pickup cells, a signal read-out circuit for reading out image signals from the cells, and a shift register circuit for enabling the read-out circuit to produce effective video signals in response to shift pulses shifted through the respective shift register stages. The image sensor circuit includes a function security circuit whereby a shift pulse may be positively shifted through the shift register stages at all times for reading out one image pickup cell at one time.
Inventors
- 👤 Inuiya Masafumi
- 👤 Masahiro Konishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:55
CPC Classifications
H; H04; H04N; H04N25/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
271 words
A solid state image sensor system comprising: a photosensitive array including a plurality of image pickup cells producing video signals; read-out means for reading out the video signals from said pickup cells; a shift register circuit associated with said reading out means and consisting of a plurality of register stages, said circuit being sequentially energized by a shift pulse shifted through said shift register circuit such that effective video signals developed by raster scanning are produced from said read-out means; delay means for delaying signals provided thereto in association with the blanking period of the raster scanning; and control means for introducing a pulse output, after the shift pulse is shifted through said shift register circuit to a pulse input terminal of said shift register circuit for recycling via said delay means; said control means comprising function security means for monitoring a first time interval commencing at the time a pulse is introduced to an input terminal of said shift register circuit, and a second time interval longer than the first time interval; said control means permitting a pulse to be introduced to an input terminal of said shift register circuit when the pulse is supplied thereto after lapse of the first time interval and before lapse of the second time interval, inhibiting the pulse from being introduced to the input terminal when the pulse is supplied to said function security means before lapse of the first time interval, and permitting the pulse to be introduced to the input terminal synchronously with lapse of the second time interval when said pulse is not supplied until lapse of the second time interval.
Claim 2
Dependent Claim
271 words
A solid state image sensor system comprising: a photosensitive array including a plurality of image pickup cells producing video signals; read-out means for reading out the video signals from said pickup cells; a shift register circuit associated with said reading out means and consisting of a plurality of register stages, said circuit being sequentially energized by a shift pulse shifted through said shift register circuit such that effective video signals developed by raster scanning are produced from said read-out means; delay means for delaying signals provided thereto in association with the blanking period of the raster scanning; and control means for introducing a pulse output, after the shift pulse is shifted through said shift register circuit to a pulse input terminal of said shift register circuit for recycling via said delay means; said control means comprising function security means for monitoring a first time interval commencing at the time a pulse is introduced to an input terminal of said shift register circuit, and a second time interval longer than the first time interval; said control means permitting a pulse to be introduced to an input terminal of said shift register circuit when the pulse is supplied thereto after lapse of the first time interval and before lapse of the second time interval, inhibiting the pulse from being introduced to the input terminal when the pulse is supplied to said function security means before lapse of the first time interval, and permitting the pulse to be introduced to the input terminal synchronously with lapse of the second time interval when said pulse is not supplied until lapse of the second time interval.
Claim 3
Dependent Claim
31 words
An arrangement in accordance with claim 1, wherein said control means comprises signal generating means for producing control signals necessary for producing image signals from the output of said delay means.
Claim 4
Dependent Claim
32 words
An arrangement in accordance with claim 2, wherein said control signals include at least one signal selected from the group consisting of a sync signal, a blanking signal and a clamp signal.
Claim 5
Dependent Claim
33 words
An arrangement in accordance with claim 1, wherein said delay means comprises a second shift register formed by a plurality of register stages connected to the last stage of said shift register circuit.
Claim 6
Dependent Claim
218 words
An arrangement in accordance with claim 1, wherein said array is a two-dimensional array forming plural horizontal rows and vertical columns of image pick-up cells; said read-out means comprises first switching means for selecting said pickup cells by horizontal rows thereof, and second switching means for reading out video signals from the image pickup cells selected by said first switching means; said shift register circuit comprises a vertical shift register circuit for sequentially enabling said first switching means and a horizontal shift register circuit for sequentially enabling said second switching means; said vertical shift register circuit shifts said pulse responsive to output from said horizontal shift register circuit; said control means further comprises a horizontal control circuit wherein the pulse output shifted through said horizontal shift register circuit is introduced to the pulse input terminal of said horizontal shift register circuit for recycling therethrough by way of a horizontal delay circuit causing a delay substantially equal to the horizontal blanking period of the raster scanning, and a vertical control circuit wherein the pulse output cycled through said vertical shift register circuit is introduced to the pulse input terminal of said vertical shift register circuit for recycling therethrough by way of a vertical delay circuit causing the delay substantially equal to the vertical blanking period of the raster scanning.
Claim 7
Dependent Claim
64 words
An arrangement in accordance with claim 5, wherein said horizontal control circuit comprises a signal forming circuit for forming control signals necessary to form video signals from the output of the delay circuit thereof, said signal forming circuit forming at least one pulse selected from the group consisting of a horizontal blanking pulse, a clamp pulse and a vertical shift register driving clock pulse.
Claim 8
Dependent Claim
50 words
An arrangement in accordance with claim 5, wherein said vertical control circuit comprises a signal forming circuit to form control signals necessary for forming video signals from the output of the delay circuit thereof, said signal forming circuit forming at least a vertical sync pulse or a vertical blanking pulse.
References Cited (Backward Citations)
US3622697A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-07 | 1989-10-07 | 1990-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-07 | 1993-10-07 | 1994-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-07 | 1997-10-07 | 1998-04-08 | $7700.00 | Window Closed / Lapsed |