US4581600A
Expired / Lapsed
US
⏱️ 0.0 years remaining
D/A converter
Assignee: Hitachi Ltd
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Filing: 1983-09-15
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Granted: 1986-04-08
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Expires: 2003-09-15
Abstract
Abstract A D/A converter comprises one or both of a first D/A converter and a second D/A converter. In the first D/A converter, n (n≧2) semiconductor devices are connected in parallel to each other between a power supply and a load resistor, gates of (n-1) semiconductor devices (called a first group of semiconductor devices) of the n semiconductor devices are connected to a common gate bias potential source, those semiconductor devices of the first group of semiconductor devices which are equal in number to the number determined by a content of high order bits of an input digital data are turned on to supply a current to the load resistor, and a voltage drop across the load resistor is outputted as an analog quantity representing the high order bits. In the second D/A converter, a gate voltage determined by a content of low order bits of the input digital data is supplied to a gate of the remaining one (called a second semiconductor device) of the n semiconductor device to supply a current to the load resistor, and a voltage drop across the load resistor is outputted as an analog quantity representing the low order bits.
Inventors
- 👤 Yuji Ito
- 👤 Toshinori Murata
- 👤 Masafumi Kazumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:07
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/68; H03M1/682; H03M1/74; H03M1/742; H03M1/747; H03M1/76; H03M1/765
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
238 words
A D/A converter for producing an analog signal from an n-bit digit signal applied thereto comprising: .sup. m current sources each having a control terminal for producing a current whose value is responsive to a voltage applied to said control terminal, where m<n; a first voltage source for producing a first DC voltage; a second voltage source for producing a second DC voltage different from said first DC voltage; biasing means for supplying said second DC voltage to said control terminals of all but a predetermined one of said current sources; m-bit decoder means for effecting operation of a number of said 2 m -1 current sources equal to the value of a m-bit digit signal applied thereto; voltage dividing means connected between said first and second voltage sources for dividing a voltage between said first and second DC voltages into 2 n-m -1 different voltages; (n-m)-bit decoder means for supplying to said control terminal of said predetermined one of said current sources one of said 2 n-m -1 voltage whose value is near said second DC voltage in the order of the number of an (n-m)-bit digit signal applied thereto; signal providing means for supplying m most significant bits and n-m least significant bits of said n bit digit signal to said m-bit decoder means and said (n-m)-bit decoder means, respectively; and summation means for summing a current of all operative current sources including said predetermined one.
Claim 2
Dependent Claim
238 words
A D/A converter for producing an analog signal from an n-bit digit signal applied thereto comprising: .sup. m current sources each having a control terminal for producing a current whose value is responsive to a voltage applied to said control terminal, where m<n; a first voltage source for producing a first DC voltage; a second voltage source for producing a second DC voltage different from said first DC voltage; biasing means for supplying said second DC voltage to said control terminals of all but a predetermined one of said current sources; m-bit decoder means for effecting operation of a number of said 2 m -1 current sources equal to the value of a m-bit digit signal applied thereto; voltage dividing means connected between said first and second voltage sources for dividing a voltage between said first and second DC voltages into 2 n-m -1 different voltages; (n-m)-bit decoder means for supplying to said control terminal of said predetermined one of said current sources one of said 2 n-m -1 voltage whose value is near said second DC voltage in the order of the number of an (n-m)-bit digit signal applied thereto; signal providing means for supplying m most significant bits and n-m least significant bits of said n bit digit signal to said m-bit decoder means and said (n-m)-bit decoder means, respectively; and summation means for summing a current of all operative current sources including said predetermined one.
Claim 3
Dependent Claim
14 words
A D/A converter according to claim 1, wherein said current sources comprise P-MOS transistors.
Claim 4
Dependent Claim
44 words
A D/A converter according to claim 1, wherein said voltage divider means comprises a plurality of resistors connected in series between said first and second voltage sources to form respective stages from which respective values of said 2 n-m -1 different voltages are provided.
Claim 5
Dependent Claim
71 words
A D/A converter according to claim 3, wherein said (n-m)-bit decoder means includes a decoder connected to receive said (n-m)-bit digit signal from said signal providing means and having 2.sup.(n-m) -1 output terminals which are respectively energized according to the value of said (n-m)-bit digit signal, and a plurality of switch devices connecting respective stages of said voltage divider to the control terminal of said predetermined one of said current sources.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-07 | 1989-10-07 | 1990-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-07 | 1993-10-07 | 1994-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-07 | 1997-10-07 | 1998-04-08 | $7700.00 | Window Closed / Lapsed |