US4338592A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High accuracy digital-to-analog converter and transient elimination system thereof
Assignee: Sipex Corp
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Filing: 1980-02-11
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Granted: 1982-07-06
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Expires: 2000-02-11
Abstract
Abstract A transient-free, high accuracy digital-to-analog converter is disclosed having a resistor network which generates a plurality of equally weighted currents selectively switched to an output bus to provide an output corresponding to the input code, in which a binary input code is decoded into a specialized code such that an incremental increase in the input code causes an additional one of the equally weighted currents to be coupled to the output bus.
Inventors
- 👤 Samuel Wilensky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:04
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08; H03M1/0863; H03M1/66; H03M1/74; H03M1/78; H03M1/785
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
162 words
A method of compensating a digital-to-analog converter of the type which includes a resistor network which provides equally weighted currents at the output nodes thereof by virtue of providing a string of serially connected trimming resistors, one end of the string being coupled to a voltage source, and main resistors, each, with the exception of the LSB main resistor, being connected at one end thereof to a junction between adjacent trimming resistors and each being selectively coupled at the other end thereof either to a load or ground, comprising the steps of trimming the main resistors starting with the main resistor corresponding to the least significant bit and working towards the main resistor corresponding to the most significant bit, and trimming a trimming resistor immediately to the less significant bit side of an over-trimmed main resistor such that the current generated by each main resistor corresponding to less significant bits generates a current equal to the current generated by the overtrimmed resistor.
Claim 2
Independent Claim
162 words
A method of compensating a digital-to-analog converter of the type which includes a resistor network which provides equally weighted currents at the output nodes thereof by virtue of providing a string of serially connected trimming resistors, one end of the string being coupled to a voltage source, and main resistors, each, with the exception of the LSB main resistor, being connected at one end thereof to a junction between adjacent trimming resistors and each being selectively coupled at the other end thereof either to a load or ground, comprising the steps of trimming the main resistors starting with the main resistor corresponding to the least significant bit and working towards the main resistor corresponding to the most significant bit, and trimming a trimming resistor immediately to the less significant bit side of an over-trimmed main resistor such that the current generated by each main resistor corresponding to less significant bits generates a current equal to the current generated by the overtrimmed resistor.
Claim 3
Dependent Claim
172 words
A transient-free high accuracy digital-to-analog converter comprising: a reference voltage source, ground, and a load; an output bus connected to said load; a resistor network including a serially-connected string of trimming resistors, one end of which being connected to said reference voltage source, and equal-current defining resistors connected at one end thereof to junctions between adjacent trimming resistors; means for selectively connecting the other ends of said equal-current defining resistors to ground or said output bus so as to generate equally weighted currents summed at said bus; and, means for converting a binary input code into a signal coupled to said selective connection means for controlling the selective connection of said equal-current defining resistors to said output bus such that an incremental increase in the binary input code causes an additional one of said equally weighted currents to be applied to said output bus, whereby overtrimming of an equal-current defining resistor corresponding to a bit may be compensated for by the trimming resistor which controls the current through all lower significant bits.
Claim 4
Dependent Claim
172 words
A transient-free high accuracy digital-to-analog converter comprising: a reference voltage source, ground, and a load; an output bus connected to said load; a resistor network including a serially-connected string of trimming resistors, one end of which being connected to said reference voltage source, and equal-current defining resistors connected at one end thereof to junctions between adjacent trimming resistors; means for selectively connecting the other ends of said equal-current defining resistors to ground or said output bus so as to generate equally weighted currents summed at said bus; and, means for converting a binary input code into a signal coupled to said selective connection means for controlling the selective connection of said equal-current defining resistors to said output bus such that an incremental increase in the binary input code causes an additional one of said equally weighted currents to be applied to said output bus, whereby overtrimming of an equal-current defining resistor corresponding to a bit may be compensated for by the trimming resistor which controls the current through all lower significant bits.
Claim 5
Dependent Claim
37 words
The converter of claim 1 wherein said reference voltage includes a reference voltage bus and wherein the resistive elements are laid out between said reference voltage bus and said output bus so as to facilitate resistor trimming.
Claim 6
Dependent Claim
31 words
The converter of claim 1 and further including a high impedence operational amplifier having an input coupled to said output bus, whereby the effect of switching on said converter is minimized.
Claim 7
Dependent Claim
43 words
The converter of claim 1 wherein said selective connection means includes a latch circuit connected to the output of said converting means; and means for reading out said latch circuit so as to actuate said selective connection means to simultaneously effect all switching.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-05 | 1986-01-04 | 1986-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-05 | 1990-01-04 | 1990-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-05 | 1994-01-04 | 1994-07-06 | $7700.00 | Window Closed / Lapsed |