US4580265A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Failure detection method and apparatus
Assignee: International Business Machines Corp
•
Filing: 1983-06-30
•
Granted: 1986-04-01
•
Expires: 2003-06-30
Abstract
Abstract A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.
Inventors
- 👤 David N. Gooding
- 👤 Stefan P. Jackowski
- 👤 James T. Moyer
- 👤 James W. Plant, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:57
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
350 words
An apparatus for detecting an abnormal circuit condition resulting in the transmission of an erroneous sequence of data from one circuit to another circuit, said data including even data bytes and odd data bytes, the even and odd data bytes each including a plurality of data bits and a parity bit, the even and odd data bytes of said data being provided to said one circuit with a predetermined parity for transmission to said another circuit, comprising: first circuit means disposed within said another circuit for developing an alternating signal, said alternating signal having a first state associated with said even data bytes and a second state associated with said odd data bytes; second circuit means disposed within said one circuit, connected to said first circuit means and responsive to said alternating signal for transmitting said even data bytes with said predetermined parity and for inverting the parity bit of said odd data bytes thereby transmitting said odd data bytes with a parity opposite to said predetermined parity; third circuit means disposed within said another circuit, connected to said first circuit means and said second circuit means and responsive to the parity bit of said even data bytes, the parity bit of said odd data bytes, and said alternating signal from said first circuit means for passing the received parity bit without inversion and generating a first output signal indicative of a non-inverted parity bit in response to said first state of said alternating signal and for re-inverting the received parity bit and generating a second output signal indicative of the re-inverted parity bit in response to said second state of said alternating signal; and parity checker means disposed within said another circuit and responsive to said first and second output signal from said third circuit means and to said plurality of data bits associated with said even and odd data bytes for generating an error check signal when the parity associated with said first or second output signal from said third circuit means and the plurality of received data bits corresponds to said parity opposite to said predetermined parity.
Claim 2
Independent Claim
350 words
An apparatus for detecting an abnormal circuit condition resulting in the transmission of an erroneous sequence of data from one circuit to another circuit, said data including even data bytes and odd data bytes, the even and odd data bytes each including a plurality of data bits and a parity bit, the even and odd data bytes of said data being provided to said one circuit with a predetermined parity for transmission to said another circuit, comprising: first circuit means disposed within said another circuit for developing an alternating signal, said alternating signal having a first state associated with said even data bytes and a second state associated with said odd data bytes; second circuit means disposed within said one circuit, connected to said first circuit means and responsive to said alternating signal for transmitting said even data bytes with said predetermined parity and for inverting the parity bit of said odd data bytes thereby transmitting said odd data bytes with a parity opposite to said predetermined parity; third circuit means disposed within said another circuit, connected to said first circuit means and said second circuit means and responsive to the parity bit of said even data bytes, the parity bit of said odd data bytes, and said alternating signal from said first circuit means for passing the received parity bit without inversion and generating a first output signal indicative of a non-inverted parity bit in response to said first state of said alternating signal and for re-inverting the received parity bit and generating a second output signal indicative of the re-inverted parity bit in response to said second state of said alternating signal; and parity checker means disposed within said another circuit and responsive to said first and second output signal from said third circuit means and to said plurality of data bits associated with said even and odd data bytes for generating an error check signal when the parity associated with said first or second output signal from said third circuit means and the plurality of received data bits corresponds to said parity opposite to said predetermined parity.
Claim 3
Dependent Claim
68 words
The apparatus of claim 1, wherein said even data bytes and said odd data bytes are received by said one circuit with odd parity, said even data bytes being transmitted from said second circuit means of said one circuit with odd parity, said second circuit means inverting the parity bit of said odd data bytes and transmitting said odd data bytes from said one circuit with even parity.
Claim 4
Dependent Claim
86 words
The apparatus of claim 2, wherein said third circuit means within said another circuit receives the parity bit of said even and odd data bytes and receives the alternating signal from said first circuit means, said third circuit means re-inverting the received parity bit in response to said second state of said alternating signal and generating said second output signal, said third circuit means not re-inverting the received parity bit in response to said first state of said alternating signal and generating said first output signal.
Claim 5
Dependent Claim
47 words
The apparatus of claim 3, wherein said parity checker means determines the parity associated with said plurality of received data bits in combination with said first or second output signal from said third circuit means and generates said error check signal when the determined parity is even.
Claim 6
Independent Claim
231 words
A method of detecting the receipt of a second piece of data when said data has been transmitted out-of-sequence relative to a first piece of data, comprising the steps of: transmitting the first piece of data with a predetermined parity, said first piece of data comprising a plurality of data bits and a parity bit; inverting a parity bit associated with the second piece of data and transmitting the second piece of data with a parity opposite to said predetermined parity, said second piece of data comprising a plurality of data bits and a parity bit; generating a clock signal having two states, a first state corresponding to said first piece of data and a second state corresponding to said second piece of data; comparing the parity bit of said first and second piece of data with the state of said clock signal, re-inverting said parity bit only when said state of said clock signal corresponds to said second state, and generating a further parity bit in response thereto; and determining a new combined parity utilizing said plurality of data bits of said first and second pieces of data and said further parity bit and generating an error check signal representative of the transmission of said second piece of data out-of-sequence relative to said first piece of data when the new combined parity is said parity opposite to said predetermined parity.
Claim 7
Independent Claim
231 words
A method of detecting the receipt of a second piece of data when said data has been transmitted out-of-sequence relative to a first piece of data, comprising the steps of: transmitting the first piece of data with a predetermined parity, said first piece of data comprising a plurality of data bits and a parity bit; inverting a parity bit associated with the second piece of data and transmitting the second piece of data with a parity opposite to said predetermined parity, said second piece of data comprising a plurality of data bits and a parity bit; generating a clock signal having two states, a first state corresponding to said first piece of data and a second state corresponding to said second piece of data; comparing the parity bit of said first and second piece of data with the state of said clock signal, re-inverting said parity bit only when said state of said clock signal corresponds to said second state, and generating a further parity bit in response thereto; and determining a new combined parity utilizing said plurality of data bits of said first and second pieces of data and said further parity bit and generating an error check signal representative of the transmission of said second piece of data out-of-sequence relative to said first piece of data when the new combined parity is said parity opposite to said predetermined parity.
References Cited (Backward Citations)
US3456239A
Cited
US3784976A
Cited
US3889236A
Cited
US3992696A
Cited
US4271521A
Cited
US4346474A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-31 | 1989-09-30 | 1990-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-31 | 1993-09-30 | 1994-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-31 | 1997-09-30 | 1998-04-01 | $7700.00 | Window Closed / Lapsed |