US4580127A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for converting analog bipolar signals to digital signals
Assignee: JET ELECTRONICS & TECHNOLOGY INCORPORATED A CORP OF DEL
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Filing: 1983-03-28
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Granted: 1986-04-01
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Expires: 2003-03-28
Abstract
Abstract An A/D converter includes a limiting circuit for limiting the amplitude of bipolar input signals. A comparator compares the amplitude limited signals with reference voltages and provides pulse output signals corresponding to the duration of each half-cycle of the bipolar signals. The pulse output signals are applied to a counter circuit which counts clock pulses for each of the half-cycle intervals to provide a digital word for each half-cycle of bipolar signal information which accurately indicates the duration of each half-cycle of the input signal. The A/D circuit is employed, in one embodiment of the present invention, with a microprocessor programmed to analyze the engine speed signals from a tachometer according to a prescribed relationship to provide output information useful for predicting when engine maintenance is required.
Inventors
- 👤 Michael G. Blowers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:08
CPC Classifications
G; G01; G01P; G01P3/00; G01P3/42; G01P3/44; G01P3/48; G01P3/481; G01P3/489; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
142 words
An analog-to-digital converter circuit for converting bipolar varying period analog signals into a digital format comprising: means for supplying bipolar analog input signals; limiter circuit means coupled to said supplying means for limiting the amplitude of each polarity of said input signals; comparator means coupled to said limiter circuit means and responsive to signals therefrom exceeding first and second reference voltage levels to provide first and second pulse output signals therefrom during a first and a second polarity, respectively, wherein the pulse width of said pulse output signals is substantially equal to the duration of each polarity of each cycle of said input signals; and counter circuit means coupled to said comparator means and responsive to said pulse output signals to provide a digital output signal for each polarity of input signal which is representative of the duration of said input signal.
Claim 2
Dependent Claim
142 words
An analog-to-digital converter circuit for converting bipolar varying period analog signals into a digital format comprising: means for supplying bipolar analog input signals; limiter circuit means coupled to said supplying means for limiting the amplitude of each polarity of said input signals; comparator means coupled to said limiter circuit means and responsive to signals therefrom exceeding first and second reference voltage levels to provide first and second pulse output signals therefrom during a first and a second polarity, respectively, wherein the pulse width of said pulse output signals is substantially equal to the duration of each polarity of each cycle of said input signals; and counter circuit means coupled to said comparator means and responsive to said pulse output signals to provide a digital output signal for each polarity of input signal which is representative of the duration of said input signal.
Claim 3
Dependent Claim
46 words
The circuit as defined in claim 1 wherein said limiter circuit comprises a diode having a cathode coupled to said supplying means and an anode coupled to ground and a second diode having an anode coupled to said supplying means and a cathode coupled to ground.
Claim 4
Dependent Claim
15 words
The circuit as defined in claim 2 wherein said first diode is a Schottky diode.
Claim 5
Dependent Claim
76 words
The circuit as defined in claim 1 wherein said comparator means comprises first and second comparator circuits with said first comparator circuit having an output terminal, an input terminal coupled to said limiting means and a reference voltage terminal coupled to a first reference voltage source and said second comparator circuit includes an input terminal coupled to said output terminal of said first comparator and a reference voltage terminal coupled to a second reference voltage source.
Claim 6
Dependent Claim
30 words
The circuit as defined in claim 4 wherein the voltage provided by said reference voltage sources is significantly less than the signals applied to said input terminals of said comparators.
Claim 7
Dependent Claim
27 words
The circuit as defined in claim 1 wherein said counter circuit means is an interval timer and said digital output signals therefrom comprise multiple bit binary words.
Claim 8
Independent Claim
121 words
A system for providing engine wear indicative information comprising: a transducer for providing analog bipolar signals representative of an engine operating parameter; limiter circuit means coupled to said transducer for limiting the amplitude of each polarity of said bipolar signals; circuit means coupled to said limiter circuit for converting signals therefrom into digital words representing the duration of each polarity of each cycle of said bipolar signals exceeding a predetermined reference level; a microprocessor coupled to said circuit means and responsive to said digital words for providing event output signals indicating predetermined engine parameter excursions; and counter means coupled to said microprocessor and responsive to said event output signals for accumulating engine parameter excursion information and for displaying such accumulated information.
Claim 9
Independent Claim
121 words
A system for providing engine wear indicative information comprising: a transducer for providing analog bipolar signals representative of an engine operating parameter; limiter circuit means coupled to said transducer for limiting the amplitude of each polarity of said bipolar signals; circuit means coupled to said limiter circuit for converting signals therefrom into digital words representing the duration of each polarity of each cycle of said bipolar signals exceeding a predetermined reference level; a microprocessor coupled to said circuit means and responsive to said digital words for providing event output signals indicating predetermined engine parameter excursions; and counter means coupled to said microprocessor and responsive to said event output signals for accumulating engine parameter excursion information and for displaying such accumulated information.
Claim 10
Independent Claim
219 words
A system for providing engine wear indicative information comprising: a transducer for providing analog bipolar input signals representative of an engine operating parameter; circuit means for converting said analog signals into digital words representing the duration of each polarity of each cycle of said bipolar signals, wherein said circuit means comprises limiter circuit means coupled to said providing means for limiting the amplitude of each polarity of said input signals, comparator means coupled to said limiter circuit means and responsive to signals therefrom exceeding first and second reference voltage levels to provide first and second pulse output signals therefrom during a first and a second polarity, respectively, wherein the pulse width of said pulse output signals is substantially equal to the duration of each polarity of each cycle of said input signals; and counter circuit means coupled to said comparator means and responsive to said pulse output signals to provide a digital output signal for each polarity of input signal which is representative of the duration of said input signal; a microprocessor coupled to said circuit means and responsive to said digital words for providing event output signals indicating predetermined engine parameter excursions; and counter means coupled to said microprocessor and responsive to said event output signals for accumulating engine parameter excursion information and for displaying such accumulated information.
Claim 11
Independent Claim
219 words
A system for providing engine wear indicative information comprising: a transducer for providing analog bipolar input signals representative of an engine operating parameter; circuit means for converting said analog signals into digital words representing the duration of each polarity of each cycle of said bipolar signals, wherein said circuit means comprises limiter circuit means coupled to said providing means for limiting the amplitude of each polarity of said input signals, comparator means coupled to said limiter circuit means and responsive to signals therefrom exceeding first and second reference voltage levels to provide first and second pulse output signals therefrom during a first and a second polarity, respectively, wherein the pulse width of said pulse output signals is substantially equal to the duration of each polarity of each cycle of said input signals; and counter circuit means coupled to said comparator means and responsive to said pulse output signals to provide a digital output signal for each polarity of input signal which is representative of the duration of said input signal; a microprocessor coupled to said circuit means and responsive to said digital words for providing event output signals indicating predetermined engine parameter excursions; and counter means coupled to said microprocessor and responsive to said event output signals for accumulating engine parameter excursion information and for displaying such accumulated information.
Claim 12
Dependent Claim
76 words
The circuit as defined in claim 8 wherein said comparator means comprises first and second comparator circuits with said first comparator circuit having an output terminal, an input terminal coupled to said limiting means and a reference voltage terminal coupled to a first reference voltage source and said second comparator circuit includes an input terminal coupled to said output terminal of said first comparator and a reference voltage terminal coupled to a second reference voltage source.
Claim 13
Dependent Claim
46 words
The circuit as defined in claim 9 wherein said limiter circuit comprises a diode having a cathode coupled to said supplying means and an anode coupled to ground and a second diode having an anode coupled to said supplying means and a cathode coupled to ground.
Claim 14
Dependent Claim
27 words
The circuit as defined in claim 10 wherein said counter circuit means is an interval timer and said digital output signals therefrom comprise multiple bit binary words.
Claim 15
Dependent Claim
15 words
The circuit as defined in claim 11 wherein said first diode is a Schottky diode.
Claim 16
Dependent Claim
30 words
The circuit as defined in claim 12 wherein the voltage provided by said reference voltage sources is signficantly less than the signals applied to said input terminals of said comparators.
Claim 17
Dependent Claim
164 words
An analog-to-digital converter circuit comprising: means for supplying analog input signals; low pass filter means coupled to said supplying means for filtering out noise frequency signals; limiter circuit means coupled to said low pass filter means for clipping input signals therefrom; a first comparator circuit means having one input terminal coupled to said limiter circuit means, an output terminal and a reference voltage input terminal; a first reference voltage source coupled to said reference voltage terminal of said first comparator whereby said first comparator provided output pulse signals representative of the duration of said analog signal which exceeds said first reference voltage; a second comparator circuit means having one input terminal coupled to said limiter circuit means, an output terminal and a reference voltage input terminal; and a second reference voltage source coupled to said reference voltage terminal of said second comparator whereby said second comparator provides output pulse signals representative of the duration of said analog signal which exceeds said second reference voltage.
Claim 18
Dependent Claim
164 words
An analog-to-digital converter circuit comprising: means for supplying analog input signals; low pass filter means coupled to said supplying means for filtering out noise frequency signals; limiter circuit means coupled to said low pass filter means for clipping input signals therefrom; a first comparator circuit means having one input terminal coupled to said limiter circuit means, an output terminal and a reference voltage input terminal; a first reference voltage source coupled to said reference voltage terminal of said first comparator whereby said first comparator provided output pulse signals representative of the duration of said analog signal which exceeds said first reference voltage; a second comparator circuit means having one input terminal coupled to said limiter circuit means, an output terminal and a reference voltage input terminal; and a second reference voltage source coupled to said reference voltage terminal of said second comparator whereby said second comparator provides output pulse signals representative of the duration of said analog signal which exceeds said second reference voltage.
Claim 19
Dependent Claim
50 words
The circuit as defined in claim 14 and further including counter circuit means having first and second input terminals coupled to said output terminals of said first and second comparators respectively and responsive to signals therefrom to provide a digital output signal therefrom representing the duration of said analog signals.
Claim 20
Dependent Claim
27 words
The circuit as defined in claim 15 wherein said counter circuit means is an interval timer and said digital output signals therefrom comprise multiple bit binary words.
Claim 21
Dependent Claim
13 words
The circuit as defined in claim 16 wherein said input signals are bipolar.
Claim 22
Dependent Claim
123 words
An analog-to-digital converter circuit for converting varying analog input signals into a digital format comprising: means for supplying varying analog input signals; comparator means coupled to said supplying means and responsive to signals therefrom exceeding first and second reference voltage levels to provide first and second pulse output signals therefrom during first and second time periods in which the pulse width of said pulse output signals is substantially equal to the duration of said input signals exceeding said first and second reference voltage levels respectively; and counter circuit means coupled to said comparator means and responsive to said pulse output signals to provide a digital output signal for each polarity of input signal which is representative of the duration of said input signal.
Claim 23
Dependent Claim
123 words
An analog-to-digital converter circuit for converting varying analog input signals into a digital format comprising: means for supplying varying analog input signals; comparator means coupled to said supplying means and responsive to signals therefrom exceeding first and second reference voltage levels to provide first and second pulse output signals therefrom during first and second time periods in which the pulse width of said pulse output signals is substantially equal to the duration of said input signals exceeding said first and second reference voltage levels respectively; and counter circuit means coupled to said comparator means and responsive to said pulse output signals to provide a digital output signal for each polarity of input signal which is representative of the duration of said input signal.
Claim 24
Dependent Claim
27 words
The circuit as defined in claim 18 wherein said counter circuit means is an interval timer and said digital output signals therefrom comprise multiple bit binary words.
Claim 25
Dependent Claim
76 words
The circuit as defined in claim 19 wherein said comparator means comprises first and second comparator circuits with said first comparator circuit having an output terminal, an input terminal coupled to said limiting means and a reference voltage terminal coupled to a first reference voltage source and said second comparator circuit includes an input terminal coupled to said output terminal of said first comparator and a reference voltage terminal coupled to a second reference voltage source.
References Cited (Backward Citations)
US3237448A
Cited
US3250901A
Cited
US3309678A
Cited
US3387120A
Cited
US3362217A
Cited
US3357239A
Cited
US3482440A
Cited
US3527086A
Cited
US3499323A
Cited
US3577194A
Cited
US3593012A
Cited
US3584507A
Cited
US3835305A
Cited
US3744300A
Cited
US3686484A
Cited
US3711686A
Cited
US3878384A
Cited
US3777555A
Cited
US3841149A
Cited
US3898875A
Cited
US3914996A
Cited
US3979579A
Cited
US4031366A
Cited
US4419654A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-31 | 1989-09-30 | 1990-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-31 | 1993-09-30 | 1994-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-31 | 1997-09-30 | 1998-04-01 | $7700.00 | Window Closed / Lapsed |