Turbine engine cycle counter

Claim 2

Structure for counting the number of times an engine is passed through a speed cycle, comprising low speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined low speed, high speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined high speed, logic means operably connected to the high and low speed sensing means and responsive thereto for providing an output signal only each time the engine passing through one of the predetermined speeds after first passing from the one predetermined speed through the other predetermined speed is sensed and counter means connected to the logic means for counting the number of said output signals from the logic means.

Claim 3

Structure for counting the number of times an engine is passed through a speed cycle, comprising low speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined low speed, high speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined high speed, logic means operably connected to the high and low speed sensing means and responsive thereto for providing an output signal only each time the engine passing down through the predetermined low speed after first passing from the predetermined low speed through the predetermined high speed is sensed and counter means connected to the logic means for counting the number of said output signals from the logic means.

Claim 4

Structure for counting the number of times an engine is passed through a speed cycle, comprising low speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined low speed, high speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined high speed, logic means operably connected to the high and low speed sensing means and responsive thereto for providing an output signal only each time the engine passing down through the predetermined low speed after first passing from the predetermined low speed through the predetermined high speed is sensed and counter means connected to the logic means for counting the number of said output signals from the logic means.

Claim 5

Structure as set forth in claim 2 and further including timing means operably connected to the high speed sensing means and means for providing an output signal to inhibit an output signal until the engine has remained at a speed above said predetermined high speed for a predetermined time.

Claim 6

Structure as set forth in claim 2 and further including a transducer positioned between the engine and at least one of the sensing means permitting sensing of a specific engine parameter as an indication of at least one of the predetermined engine speeds.

Claim 7

Structure for counting the number of times an engine is passed through a speed cycle, comprising low speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined low speed including means for providing a low speed reference signal, means for providing a signal proportional to engine speed and a low speed comparator for comparing the low speed reference signal and signal proportional to engine speed conneCted to the means for providing a low speed reference signal and the means for providing a signal proportional to engine speed for providing an output signal when the signal proportional to engine speed is above the low speed reference signal, high speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined high speed including means for providing a high speed reference signal and a high speed comparator for comparing the high speed reference signal and signal proportional to engine speed connected to the means for providing a high speed reference signal and the means for providing a signal proportional to engine speed for providing an output signal when the signal proportional to engine speed is above the high speed reference signal and means operably connected to the high and low speed comparators for providing an output signal only each time the engine passes down through the predetermined low speed after first passing from the predetermined low speed through the predetermined high speed including a logic circuit having a one-shot multivibrator, a bi-stable multivibrator, a switch, an amplifier and a counter in series providing a single count on removal of the low speed comparator and the high speed comparator output signals from the one-shot multivibrator.

Claim 8

Structure for counting the number of times an engine is passed through a speed cycle, comprising low speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined low speed including means for providing a low speed reference signal, means for providing a signal proportional to engine speed and a low speed comparator for comparing the low speed reference signal and signal proportional to engine speed conneCted to the means for providing a low speed reference signal and the means for providing a signal proportional to engine speed for providing an output signal when the signal proportional to engine speed is above the low speed reference signal, high speed sensing means operably connected to the engine for sensing the passing of the engine through a predetermined high speed including means for providing a high speed reference signal and a high speed comparator for comparing the high speed reference signal and signal proportional to engine speed connected to the means for providing a high speed reference signal and the means for providing a signal proportional to engine speed for providing an output signal when the signal proportional to engine speed is above the high speed reference signal and means operably connected to the high and low speed comparators for providing an output signal only each time the engine passes down through the predetermined low speed after first passing from the predetermined low speed through the predetermined high speed including a logic circuit having a one-shot multivibrator, a bi-stable multivibrator, a switch, an amplifier and a counter in series providing a single count on removal of the low speed comparator and the high speed comparator output signals from the one-shot multivibrator.

Claim 9

Structure as set forth in claim 5 and further including means for providing a time reference signal and a timing comparator connected to the means for providing a time reference signal and between the high speed comparator and the logic circuit for permitting signals to pass from the high speed comparator to the logic circuit only after the engine has operated above the predetermined high speed for a predetermined time.

Claim 10

Structure as set forth in claim 5 and further including a frequency to voltage transducer positioned between the means for providing a signal proportional to engine speed and the comparators.

Claim 11

Structure for counting the number of times an engine is passed through a speed cycle, comprising means for providing a low speed reference signal, means for providing a high speed reference signal, means for providing a signal proportional to engine speed, a low speed comparator connected to the means for providing a low speed reference signal and to the means for providing a signal proportional to engine speed for providing a low speed comparator output signal when the signal proportional to engine speed is greater than the low speed reference signal, a high speed comparator connected to the means for providing a high speed reference signal and to the means for providing a signal proportional to engine speed for providing a high speed comparator output signal when the signal proportional to engine speed is greater than the high speed reference signal, a logic circuit connected to the low speed and high speed comparators operable to provide a logic circuit output signal on receiving a first low speed comparator output signal from the low speed comparator, a high speed comparator output signal from the high speed comparator and a subsequent signal from the low speed comparator indicating passage of the engine speed back through the low speed reference, and a counter connected to the logic circuit for providing a single count in response to each said logic circuit output signal.

Claim 12

Structure for counting the number of times an engine is passed through a speed cycle, comprising means for providing a low speed reference signal, means for providing a high speed reference signal, means for providing a signal proportional to engine speed, a low speed comparator connected to the means for providing a low speed reference signal and to the means for providing a signal proportional to engine speed for providing a low speed comparator output signal when the signal proportional to engine speed is greater than the low speed reference signal, a high speed comparator connected to the means for providing a high speed reference signal and to the means for providing a signal proportional to engine speed for providing a high speed comparator output signal when the signal proportional to engine speed is greater than the high speed reference signal, a logic circuit connected to the low speed and high speed comparators operable to provide a logic circuit output signal on receiving a first low speed comparator output signal from the low speed comparator, a high speed comparator output signal from the high speed comparator and a subsequent signal from the low speed comparator indicating passage of the engine speed back through the low speed reference, and a counter connected to the logic circuit for providing a single count in response to each said logic circuit output signal.

Claim 13

Structure as set forth in claim 8 and further including means for developing a time reference signal and a timing comparator connected to the high speed comparator and the means for developing a time reference signal for permitting an output signal from the high speed comparator to the logic circuit only after an output signal from the high speed comparator has been present for a predetermined time.

Claim 14

Structure as set forth in claim 8 wherein the means for developing a signal proportional to engine speed includes a tachometer generator connected to the engine operable to rotate at a speed proportional to engine speed and a frequency to voltage level converter connectEd between the tachometer generator and the comparators.

Claim 17

The method as set forth in claim 11 and further providing a reference time signal and permitting a high speed output signal indicating the passing of the engine through a speed greater than the high speed reference signal only after the engine speed has been maintained higher than the high speed reference signal for a predetermined time.

Claim 18

The method as set forth in claim 11 wherein the signal proportional to engine speed is first developed as an alternating frequency proportional to engine speed and subsequently converted into a voltage level signal.