Patent US4580103A successfully refreshed from Google Patents.
US4580103A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Amplifier circuit arrangement for eliminating input signal offset in the output
Assignee: Nokia Bell Labs
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Filing: 1984-06-22
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Granted: 1986-04-01
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Expires: 2004-06-22
Abstract
Abstract In a semiconductor integrated circuit comprising an amplifier for detecting the presence of a carrier on an incoming wave signal, in order to suppress dc offset in the incoming wave and at the same time minimize any inherent input amplifier offset, the amplifier is supplied with a switched capacitor input network connected between a first input terminal of the amplifier and a circuit input terminal for receiving an incoming signal, and with a switched capacitor feedback network connected between an output terminal of the amplifier and a second (opposite polarity) input terminal of the amplifier.
Inventors
- 👤 Michael F. Tompsett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:30
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/303
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
142 words
In a semiconductor integrated circuit, a carrier detection circuit portion comprising: (a) a circuit portion input terminal; (b) an amplifier having a pair of first and second input terminals of opposite polarities and an amplifier output terminal; and (c) an input network comprising: (1) a first clocked transistor ohmically connected between a reference terminal and the first input terminal of the amplifier; (2) a second complementary clocked transistor connected between the circuit input terminal and an internal node; (3) a first capacitor connected between the internal node and the reference terminal; and (4) a second capacitor connected between the internal node and the first input terminal of the amplifier, whereby during operation the voltage developed at the amplifier output terminal is substantially free of any dc offset that is present in an incoming ac signal applied to the circuit portion input terminal.
Claim 2
Dependent Claim
142 words
In a semiconductor integrated circuit, a carrier detection circuit portion comprising: (a) a circuit portion input terminal; (b) an amplifier having a pair of first and second input terminals of opposite polarities and an amplifier output terminal; and (c) an input network comprising: (1) a first clocked transistor ohmically connected between a reference terminal and the first input terminal of the amplifier; (2) a second complementary clocked transistor connected between the circuit input terminal and an internal node; (3) a first capacitor connected between the internal node and the reference terminal; and (4) a second capacitor connected between the internal node and the first input terminal of the amplifier, whereby during operation the voltage developed at the amplifier output terminal is substantially free of any dc offset that is present in an incoming ac signal applied to the circuit portion input terminal.
Claim 3
Dependent Claim
36 words
The circuit portion of claim 1 in which the capacitance from the internal node to the reference terminal is substantially equal to the capacitance from the internal node to the first input terminal of the amplifier.
Claim 4
Dependent Claim
120 words
The circuit portion of claim 1 further comprising: (a) a third clocked transistor, clocked in the same way as the first transistor, connected between the amplifier output terminal and the second input terminal of the amplifier; (b) a third capacitor connected between the amplifier output terminal and a second internal node which is ohmically coupled to the second input terminal of the amplifier; and (c) a fourth capacitor connected between the second internal node and the reference terminal, whereby the operating gain of the amplifier is approximately equal to the ratio of the capacitance of the fourth to the third capacitor, and whereby the inherent input offset of the amplifier appears on the output terminal without substantial gain above unity.
Claim 5
Dependent Claim
35 words
The circuit portion of claim 3 in which the reciprocal of the capacitance of the fourth capacitor is substantially equal to the sum of the reciprocals of the capacitances of the first and second capacitors.
Claim 6
Dependent Claim
28 words
The circuit portion of claim 4 in which the capacitance of the fourth capacitor is at least a factor of ten greater than that of the third capacitor.
Claim 7
Dependent Claim
28 words
The circuit portion of claim 3 in which the capacitance of the fourth capacitor is at least a factor of ten greater than that of the third capacitor.
Claim 8
Dependent Claim
75 words
In a semiconductor integrated circuit for detecting the presence of a carrier wave on an incoming wave signal, a carrier detection circuit portion comprising: (a) a circuit portion input terminal; (b) an amplifier having a pair of first and second input terminals of opposite polarities and an amplifier output terminal; and (c) an input network comprising: (1) a first clocked transistor conductively connected between a reference terminal and the first input terminal of the amplifier;
Claim 9
Dependent Claim
75 words
In a semiconductor integrated circuit for detecting the presence of a carrier wave on an incoming wave signal, a carrier detection circuit portion comprising: (a) a circuit portion input terminal; (b) an amplifier having a pair of first and second input terminals of opposite polarities and an amplifier output terminal; and (c) an input network comprising: (1) a first clocked transistor conductively connected between a reference terminal and the first input terminal of the amplifier;
Claim 10
Dependent Claim
16 words
(2) a second complementary clocked transistor connected between the circuit input terminal and an internal node;
Claim 11
Dependent Claim
16 words
(2) a second complementary clocked transistor connected between the circuit input terminal and an internal node;
Claim 12
Dependent Claim
61 words
(3) a first capacitor connected between the internal node and the reference terminal; and (4) a second capacitor connected between the internal node and the first input terminal of the amplifier, whereby during operation the voltage developed at the amplifier output terminal is substantially free of any dc offset in the incoming signal when applied to the circuit portion input terminal.
Claim 13
Dependent Claim
61 words
(3) a first capacitor connected between the internal node and the reference terminal; and (4) a second capacitor connected between the internal node and the first input terminal of the amplifier, whereby during operation the voltage developed at the amplifier output terminal is substantially free of any dc offset in the incoming signal when applied to the circuit portion input terminal.
Claim 14
Dependent Claim
36 words
The circuit portion of claim 7 in which the capacitance from the internal node to the reference terminal is substantially equal to the capacitance from the internal node to the first input terminal of the amplifier.
Claim 15
Dependent Claim
119 words
The circuit portion of claim 7 further comprising: (a) a third clocked transistor, clocked in the same way as the first transistor, connected between the amplifier output terminal and the second input terminal of the amplifier; (b) a third capacitor connected between the amplifier output terminal and a second internal node which is ohmically coupled to the second input terminal of the amplifier; and (c) a fourth capacitor connected between the second internal node and the reference terminal, whereby the operating gain of the amplifier is approximately equal to the ratio of the capacitance of the fourth to the third capacitor, whereby the inherent input offset of the amplifier appears on the output terminal without substantial gain above unity.
Claim 16
Dependent Claim
23 words
The circuit portion of claim 9 in which the capacitance of the first capacitor is substantially equal to that of the second capacitor.
Claim 17
Dependent Claim
28 words
The circuit portion of claim 10 in which the capacitance of the fourth capacitor is at least a factor of ten greater than that of the third capacitor.
Claim 18
Dependent Claim
28 words
The circuit portion of claim 9 in which the capacitance of the fourth capacitor is at least a factor of ten greater than that of the third capacitor.
Claim 19
Dependent Claim
106 words
In a semiconductor integrated circuit: (a) a signal input terminal for receiving an input signal; (b) an amplifier; and (c) an input network comprising (1) first and second capacitors each having a terminal connected to a common node, the second capacitor having another terminal which is connected to an input terminal of the amplifier, the first capacitor having another terminal which is connected to a reference terminal, (2) a first clocked transistor, connected for periodically connected the input terminal of the amplifier directly to a reference terminal, and (3) a second, complementary clocked transistor, connected for periodically connecting the signal input terminal to the common node.
Claim 20
Dependent Claim
106 words
In a semiconductor integrated circuit: (a) a signal input terminal for receiving an input signal; (b) an amplifier; and (c) an input network comprising (1) first and second capacitors each having a terminal connected to a common node, the second capacitor having another terminal which is connected to an input terminal of the amplifier, the first capacitor having another terminal which is connected to a reference terminal, (2) a first clocked transistor, connected for periodically connected the input terminal of the amplifier directly to a reference terminal, and (3) a second, complementary clocked transistor, connected for periodically connecting the signal input terminal to the common node.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-31 | 1989-09-30 | 1990-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-31 | 1993-09-30 | 1994-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-31 | 1997-09-30 | 1998-04-01 | $7700.00 | Window Closed / Lapsed |