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US4577293A
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Distributed, on-chip cache
Assignee: International Business Machines Corp
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Filing: 1984-06-01
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Granted: 1986-03-18
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Expires: 2004-06-01
Abstract
Abstract The cache reload time in small computer systems is improved by using a distributed cache located on the memory chips. The large bandwidth between the main memory and cache is the usual on-chip interconnecting lines which avoids pin input/output problems. This distributed cache is achieved by the use of communicating random access memory chips of the type incorporating a primary port (10) and a secondary port (14). Ideally, the primary and secondary ports can run totally independently of each other. The primary port functions as in a typical dynamic random access memory and is the usual input/output path for the memory chips. The secondary port, which provides the distributed cache, makes use of a separate master/slave row buffer (15) which is normally isolated from the sense amplifier/latches. Once this master/slave row buffer is loaded, it can be accessed very fast, and the large bandwidth between the main memory array and the on-chip row buffer provides a very fast reload time for a cache miss.
Inventors
- 👤 Richard E. Matick
- 👤 Daniel T. Ling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:58
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0864; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1063; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
125 words
A distributed, on-chip cache comprising a secondary row port buffer on a plurality of dynamic random access memory chips, each of said memory chips comprising a primary port for access to a storage array on the chip, said secondary row port buffer, and isolation means for providing a normally isolated connection between said secondary row port buffer and said storage array, said secondary row port buffer comprising a master register, a slave register, and parallel input/output driver means for providing access to said slave register, said master register being loaded from said storage array through said isolation means and subsequently when said secondary row port buffer is isolated from said storage array by said isolation means, said slave register being loaded from said master register.
Claim 2
Dependent Claim
125 words
A distributed, on-chip cache comprising a secondary row port buffer on a plurality of dynamic random access memory chips, each of said memory chips comprising a primary port for access to a storage array on the chip, said secondary row port buffer, and isolation means for providing a normally isolated connection between said secondary row port buffer and said storage array, said secondary row port buffer comprising a master register, a slave register, and parallel input/output driver means for providing access to said slave register, said master register being loaded from said storage array through said isolation means and subsequently when said secondary row port buffer is isolated from said storage array by said isolation means, said slave register being loaded from said master register.
Claim 3
Dependent Claim
78 words
A distributed, on-chip cache as recited in claim 1 wherein said input/output driver means includes a decoder connected to said slave register for decoding n out of N bits where N is the width of a row in said storage array and N is a number less than N, addressing means connected to said decoder for addressing n bits, and n tri-state drivers connected to said decoder to provide n output bits from said secondary row port buffer.
Claim 4
Dependent Claim
40 words
A distributed, on-chip cache as recited in claim 2 wherein said decoder is a bidirectional device, further comprising n tri-state receivers connected to said decoder for reading data into said slave register at a location determined by said addressing means.
Claim 5
Dependent Claim
60 words
A distributed, on-chip cache as recited in claim 3 wherein said storage array includes sense amplifiers for sensing the contents of an addressed row of said storage array, further comprising N drivers connected between the outputs of said slave register and said sense amplifiers for writing the contents of said slave register into an addressed row of said storage array.
Claim 6
Dependent Claim
37 words
A distributed, on-chip cache as recited in claim 1 wherein each of said master register and said slave register are composed of N master/slave latches where N is the width of a row in said storage array.
Claim 7
Dependent Claim
34 words
A distributed, on-chip cache as recited in claim 5 wherein said master/slave latches of said master and slave registers are interconnected to permit the simultaneous exchange of data between said master and slave registers.
Claim 8
Dependent Claim
72 words
A distributed, on-chip cache as recited in claim 1 wherein said plurality of dynamic random access memory chips are organized in a plurality of banks of chips, further comprising bank select means connected to each of said banks of chips for addressing a single one of said banks of chips, the output of said cache being the combined output of the secondary row port buffers of each chip in an addressed bank.
Claim 9
Dependent Claim
141 words
A distributed, on-chip cache as recited in claim 7 further comprising virtual address register means for storing a virtual address of data, directory means for storing the full virtual addresses of data in said distributed cache, comparing means for comparing the address in said virtual address register means with the addresses in said directory means to generate an enable cache signal if the address stored in the virtual address register means matches an address in said directory means, said bank select means including decoding means responsive to a portion of said virtual address in said virtual address register means to generate a block select signal, and gating means responsive to said enable cache signal and said block select signal to select that portion of the distributed cache containing the data identified by the vitual address in said virtual address register means.
Claim 10
Dependent Claim
74 words
A distributed, on-chip cache as recited in claim 8 futher comprising least recently used means in said directory means for determining whether the addressed data is in the master register or the slave register of said secondary row port buffer, and transfer means operative in the event the addressed data is in said master register to first transfer the data from said master register to said slave register before generating said enable cache signal.
References Cited (Backward Citations)
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Cited
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Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-17 | 1989-09-16 | 1990-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-17 | 1993-09-16 | 1994-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-17 | 1997-09-16 | 1998-03-18 | $7700.00 | Window Closed / Lapsed |