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US4577231A
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US
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High sensitivity solid-state imaging device
Assignee: Hitachi Ltd
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Filing: 1983-03-17
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Granted: 1986-03-18
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Expires: 2003-03-17
Abstract
Abstract Disclosed is a two-dimensionally arrayed solid-state imaging device for a television camera having a photodiode array arranged at a photo-sensing section and a readout horizontal register constructed by a charge transfer device (CTD) such as a BCD, CCD or BBD. An inverter circuit is provided for each of the vertical signal lines. An input of the inverter circuit is connected to a vertical signal line drain of at least one transfer transistor arranged between the vertical signal line and the CTD, and an output of the inverter circuit is connected to a gate of the transfer transistor. Transfer efficiency is improved by the insertion of the inverter circuit and fixed pattern noise is substantially reduced by supplying bias currents.
Inventors
- 👤 Shinya Ohba
- 👤 Haruhisa Ando
- 👤 Masaaki Nakai
- 👤 Toshifumi Ozaki
- 👤 Koichi Seki
- 👤 Kenji Takahashi
- 👤 Toshiyuki Akiyama
- 👤 Iwao Takemoto
- 👤 Takuya Imaide
- 👤 Akihide Okuda
- 👤 Masaharu Kubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:32
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/18; H04; H04N; H04N25/00; H04N25/70; H04N25/76
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
255 words
A high sensitivity solid-state imaging device wherein a photo-sensing section is constructed of a MOS-type sensor in which picture elements each comprised of a photodiode and a switching MOS transistor are arrayed in the form of a matrix, wherein signal outputs of the respective picture elements of said MOS-type sensor are transferred to a CTD (charge transfer device) through vertical signal lines, and wherein the signal outputs are read out by said CTD, said imaging device comprising: signal-transfer means for causing bias charges to enter into said vertical signal lines so as to mix them with signal charges on said vertical signal lines and for causing the mixed signal charges to be transferred into said CTD, said signal-transfer means including a first gate MOS transistor which is connected between the vertical signal line and said CTD; reset means for setting a potential of said vertical signal line to a predetermined reference voltage before the bias charges enter into said vertical signal line, said reset means including second and third gate MOS transistors which are connected in series between said first gate MOS transistor and said vertical signal line; a reset gate element which is connected between a juncture of said first and second gate MOS transistors and a reset-voltage line; and an inverter circuit having a first input terminal thereof connected to a corresponding one of said vertical signal lines, a second input terminal connected to a common voltage line, and an output terminal connected to the gate of the corresponding third gate MOS transistor.
Claim 2
Dependent Claim
255 words
A high sensitivity solid-state imaging device wherein a photo-sensing section is constructed of a MOS-type sensor in which picture elements each comprised of a photodiode and a switching MOS transistor are arrayed in the form of a matrix, wherein signal outputs of the respective picture elements of said MOS-type sensor are transferred to a CTD (charge transfer device) through vertical signal lines, and wherein the signal outputs are read out by said CTD, said imaging device comprising: signal-transfer means for causing bias charges to enter into said vertical signal lines so as to mix them with signal charges on said vertical signal lines and for causing the mixed signal charges to be transferred into said CTD, said signal-transfer means including a first gate MOS transistor which is connected between the vertical signal line and said CTD; reset means for setting a potential of said vertical signal line to a predetermined reference voltage before the bias charges enter into said vertical signal line, said reset means including second and third gate MOS transistors which are connected in series between said first gate MOS transistor and said vertical signal line; a reset gate element which is connected between a juncture of said first and second gate MOS transistors and a reset-voltage line; and an inverter circuit having a first input terminal thereof connected to a corresponding one of said vertical signal lines, a second input terminal connected to a common voltage line, and an output terminal connected to the gate of the corresponding third gate MOS transistor.
Claim 3
Dependent Claim
20 words
A high sensitivity solid-state imaging device according to claim 1, wherein the gain of said inverter circuit is above 6.
Claim 4
Dependent Claim
86 words
A high sensitivity solid-state imaging device according to claim 1, wherein said inverter circuit includes a depletion type MOS transistor as a load and a driver MOS transistor, the source and gate of said depletion type MOS transistor and the drain of said driver MOS transistor each being connected to the gate of the corresponding third gate MOS transistor, and the gate and source of said driver MOS transistor being connected to the corresponding one of said vertical signal lines and said common voltage line, respectively.
Claim 5
Dependent Claim
96 words
A high sensitivity solid-state imaging device according to claim 1, wherein said inverter circuit includes an enhancement type transistor as a load and a driver MOS transistor, the source of said enhancement type transistor and the drain of said driver MOS transistor each being connected to the gate of the corresponding third gate MOS transistor, the gate and drain of said enhancement type transistor being connected to each other, and the gate and source of said driver MOS transistor being connected to the corresponding one of said vertical signal lines and said common voltage line, respectively.
Claim 6
Dependent Claim
79 words
A high sensitivity solid-state imaging device according to claim 1, wherein said inverter circuit includes a poly-Si and/or diffusion layer resistor as a load and a driver MOS transistor, the gate of said driver MOS transistor being connected to said resistor and the gate of the corresponding third gate MOS transistor, respectively, and the gate and source of said driver MOS transistor being connected to the corresponding one of said vertical signal line and said common voltage line, respectively.
Claim 7
Dependent Claim
31 words
A high sensitivity solid-state imaging device according to claim 1, further comprising a capacitor connected between said second and third gate MOS transistors storing charges being used as said bias charges.
Claim 8
Dependent Claim
32 words
A high sensitivity solid-state imaging device according to claim 1, further comprising another inverter circuit, the output terminal of which is connected to the gate of the corresponding second gate MOS transistor.
Claim 9
Dependent Claim
79 words
A high sensitivity solid-state imaging device according to claim 1, wherein at least two CTDs are coupled to said each vertical signal line to construct first and second read-out channels by means of the first and second CTDs, and means is comprised for transferring the signal outputs to the first channel in a first half of a horizontal blanking period and for transferring the signal outputs to the second channel in a latter half of the horizontal blanking period.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-17 | 1989-09-16 | 1990-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-17 | 1993-09-16 | 1994-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-17 | 1997-09-16 | 1998-03-18 | $7700.00 | Window Closed / Lapsed |