US4577180A
Expired / Lapsed
US
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Digital data converting method and apparatus thereof
Assignee: Sony Corp
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Filing: 1984-11-20
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Granted: 1986-03-18
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Expires: 2004-11-20
Abstract
Abstract A digital signal is divided into a series of base words with each m bits of data. Each base word is converted to a converted word having n bits of data, wherein each of n and m is an integer and n is greater than m and the converted word has a predetermined maximum number of consecutive digital zeroes. The value of every odd-numbered bits of said converted word is detected. The converted word is controlled in response to the result of the detection and modulated as an NRZI (non-return to zero, inverted)-coded digital signal with a DC component of zero.
Inventors
- 👤 Shinichi Fukuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:20
CPC Classifications
H; H03; H03K; H03K7/00; H03M; H03M7/00; H03M7/14; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
134 words
A method for converting a digital signal into an NRZI (non-return to zero, inverted)-coded signal, the method comprising the steps of: dividing a base digital signal into a series of base words with each m bits of data; converting said base digital signal into a converted digital signal by matching a converted word with each said base word, each said converted word having n bits of data, wherein n is greater than m and said converted digital signal has a predetermined maximum number of consecutive digital zeroes; detecting if the value of every odd-numbered bits of said converted word is digital zero; producing a detecting signal according to the result of said detecting; controlling said converted word in response to said detecting signal; and modulating said converted digital signal as an NRZI-coded digital signal.
Claim 2
Independent Claim
134 words
A method for converting a digital signal into an NRZI (non-return to zero, inverted)-coded signal, the method comprising the steps of: dividing a base digital signal into a series of base words with each m bits of data; converting said base digital signal into a converted digital signal by matching a converted word with each said base word, each said converted word having n bits of data, wherein n is greater than m and said converted digital signal has a predetermined maximum number of consecutive digital zeroes; detecting if the value of every odd-numbered bits of said converted word is digital zero; producing a detecting signal according to the result of said detecting; controlling said converted word in response to said detecting signal; and modulating said converted digital signal as an NRZI-coded digital signal.
Claim 3
Independent Claim
106 words
A method for converting a digital signal into an NRZI-coded signal, the method comprising the steps of: dividing a base digital signal into a series of base words with each eight bits of data; converting each said base word into a converted word having ten bits of data; detecting if the value of every odd-numbered bits of said converted word is digital zero; producing a detecting signal in response to a parity of said digital value in every odd-numbered bits of said converted word; controlling the first bit of said converted word in response to said detecting signal; and modulating said converted word into an NRZI-code.
Claim 4
Independent Claim
106 words
A method for converting a digital signal into an NRZI-coded signal, the method comprising the steps of: dividing a base digital signal into a series of base words with each eight bits of data; converting each said base word into a converted word having ten bits of data; detecting if the value of every odd-numbered bits of said converted word is digital zero; producing a detecting signal in response to a parity of said digital value in every odd-numbered bits of said converted word; controlling the first bit of said converted word in response to said detecting signal; and modulating said converted word into an NRZI-code.
Claim 5
Independent Claim
146 words
An apparatus for converting a digital signal into an NRZI-coded signal, the apparatus comprising: dividing means for dividing a base digital signal into a series of base words with each m bits of data; converting means for converting said base digital signal into a converted digital signal by matching a converted word with each said base word, each said converted word having n bits of data, wherein n is greater than m and said converted digital signal has a predetermined maximum number of consecutive digital zeroes; detecting means for detecting if the value of every odd-numbered bits of said converted word is digital zero; p1 producing means for producing a detecting signal according to the result of said detecting; controlling means for controlling said converted word in response to said detecting signal; and generating means for generating said converted digital signal as an NRZI-coded digital signal.
Claim 6
Independent Claim
146 words
An apparatus for converting a digital signal into an NRZI-coded signal, the apparatus comprising: dividing means for dividing a base digital signal into a series of base words with each m bits of data; converting means for converting said base digital signal into a converted digital signal by matching a converted word with each said base word, each said converted word having n bits of data, wherein n is greater than m and said converted digital signal has a predetermined maximum number of consecutive digital zeroes; detecting means for detecting if the value of every odd-numbered bits of said converted word is digital zero; p1 producing means for producing a detecting signal according to the result of said detecting; controlling means for controlling said converted word in response to said detecting signal; and generating means for generating said converted digital signal as an NRZI-coded digital signal.
Claim 7
Independent Claim
156 words
An apparatus for converting a digital base signal into an NRZI-coded signal having a DC component substantially equal to zero and a predetermined maximum time between level transitions, the apparatus comprising: dividing means for dividing a base digital signal into a series of base words with each m bits of data; memory means for converting said base word into a converted word having n bits of data, wherein n is greater than m and said converted word has a predetermined maximum number of consecutive digital zeroes; detecting means for detecting if the digital value of every odd-numbered bits of said converted word is digital zero and for producing a detecting signal in response to a parity of said digital value in every odd-numbered bits of said converted word; controlling means for inverting the first bit of said converted word in response to said detecting signal; and modulating means for modulating said converted word into an NRZI-coded.
Claim 8
Independent Claim
156 words
An apparatus for converting a digital base signal into an NRZI-coded signal having a DC component substantially equal to zero and a predetermined maximum time between level transitions, the apparatus comprising: dividing means for dividing a base digital signal into a series of base words with each m bits of data; memory means for converting said base word into a converted word having n bits of data, wherein n is greater than m and said converted word has a predetermined maximum number of consecutive digital zeroes; detecting means for detecting if the digital value of every odd-numbered bits of said converted word is digital zero and for producing a detecting signal in response to a parity of said digital value in every odd-numbered bits of said converted word; controlling means for inverting the first bit of said converted word in response to said detecting signal; and modulating means for modulating said converted word into an NRZI-coded.
Claim 9
Dependent Claim
48 words
An apparatus according to claim 4, wherein said detecting means comprisis logic means for generating said detecting signal in response to a parity of said digital value in every odd-numbered bits of said converted word and a memory circuit for holding said detecting signal during every converting cycle.
Claim 10
Dependent Claim
22 words
An apparatus according to claim 5, wherein said logic means includes an exclusive-OR circuit and said memory circuit includes a flip-flop circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-03-17 | 1989-09-16 | 1990-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-03-17 | 1993-09-16 | 1994-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-03-17 | 1997-09-16 | 1998-03-18 | $7700.00 | Window Closed / Lapsed |