US4575826B1 - - Google Patents
Abstract
Abstract A refresh generator system (5) for a dynamic memory (3) in a data processing system, including a processor (1) which is responsive to a hold request signal (HRQ) to relinquish control of the local bus and generate a hold acknowledge signal (HLDA), comprises logic means (14,11.10,13) to generate a hold request signal in response to an output from a refresh timer circuit (6). A logic circuit (16) is responsive to a hold request, a corresponding hold acknowledge, and the timer signal to generate a refresh control signal (REFR). This signal generates a refresh signal for the memory control circuits, increments a counter circuit (19) and initiates operation of a sequencer circuit (22). The sequencer then gates the output of the counter circuit to provide a memory row address and thereafter provides a memory read output (-MEMR) to refresh the memory row defined by the address and lastly resets the circuit to terminate the hold request signal.
Inventors
- 👤 E Dean Mark
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |