Programmable interface memory

Claim 2

A programmable digital memory operative in response to programmed instructions from a source of instructions to transfer digital data words between itself and at least one data handling unit external thereto, said digital memory comprising: a bulk memory partitioned into a plurality of memory sections; a plurality of memory address generators coupled correspondingly to said plurality of memory sections with each memory address generator being operative, simultaneously with and independently of the other memory address generators of said plurality, to control memory address sequencing of its corresponding memory section for the transfer of digital data words, corresponding to said sequenced addresses, between said memory section and a selected data handling unit, and to generate at least one signal representative of the state of operation thereof; and memory control logic circuitry operative in response to said programmed instructions to distribute each programmed instruction to a correspondingly designated memory address generator in accordance with said signals representative of the states of operation thereof for governing the memory address sequencing operations performed thereby.

Claim 3

The programmable digital memory in accordance with claim 1 wherein each partitioned memory section comprises a plurality of memory subsections having commonly addressable memory locations for time-multiplexing data word transfer operations; and wherein each memory address generator includes memory address sequencing apparatus for storing selected blocks of digital data words in corresponding blocks of memory locations, comprising a set of commonly addressable memory locations of said memory subsections, in accordance with desired time-multiplexed memory address accessing sequences correspondingly predetermined therefor.

Claim 4

The programmable digital memory in accordance with claim 2 wherein each partitioned memory section comprises an array of memory locations with one addressable index of each of said memory locations being the address of the memory subsection thereof and another addressable index of each of said memory locations being the address of the commonly addressable memory location thereof, said array of memory locations being further subdivided into indexed addressable blocks and subblocks of memory locations to facilitate the time-multiplexed block data word transfer operations, said subblocks comprising the commonly addressable memory locations of the plurality of memory subsections.

Claim 5

The programmable digital memory in accordance with claim 3 wherein the memory address sequencing apparatus of each memory address generator comprises: a first logic circuit for generating digital timing signals associated with the time-multiplexed memory addressing operations; a second logic circuit for generating digital timing signals associated with the memory address sequence set forth in the programmed instruction distributed thereto; a first counter circuit for generating the address sequence for the memory subsections in connection with the time-multiplexed transfer of the blocks of digital data words as governed by said programmed instruction; a second counter circuit for counting the number of digital data words being transferred in a transfer operation and for generating a signal indicative of the last word transferred in said transfer operation as governed by said programmed instruction; a third counter circuit governed by said programmed instruction for generating the memory address sequence for the memory subblocks in connection with a block transfer operation and for generating a signal indicative of the last subblock transferred in said block transfer operation; a fourth counter circuit governed by said programmed instruction for generating the memory address sequence for the memory blocks in connection with a multiple block transfer operation and for generating a signal indicative of the last block transferred in said multiple block transfer operation; and a third logic circuit for interacting said signals generated by the aforementioned circuits together and with said programmed instruction in accordance with a predetermined logical arrangement to enable and coordinate the operations of said first through fourth counter circuits, said third logic circuit further operative to generate signals indicative of the operational states of the memory address generator.

Claim 6

The programmable digital memory in accordance with claim 1 including an input switching circuit selectively operative to couple any memory section of the plurality to any one of a plurality of source data handling units external thereto in accordance with the programmed instructions for collecting and storing digital data words transferred therefrom.

Claim 7

The programmed digital memory in accordance with claim 5 wherein the input switching circuit includes means for selectively coupling more than one memory section correspondingly to more than one source data handling unit; and wherein said more than one memory sections being operative under the direction of their memory address generators to simultaneously collect and store digital data words from the source data handling units correspondingly coupled thereto.

Claim 8

The programmed digital memory in accordance with claim 5 including an input data ready logic circuit governed by the signals representative of the states of operation of the plurality of memory address generators and the programmed instructions to generate input permissive signals, each indicating that a selected memory section is available to collect and store digital words from the chosen source data handling unit correspondingly coupled thereto by the input switching circuit.

Claim 9

The programmed digital memory in accordance with claim 1 including an output switching circuit selectively operative to couple any memory section of the plurality to any of one of a plurality of destination data handling units in accordance with the programmed instructions for accessing and transferring digital data words thereto.

Claim 10

The programmed digital memory in accordance with claim 8 wherein the output switching circuit includes means for selectively coupling more than one memory section correspondingly to more than one destination data handling unit; and wherein said more than one memory sections being operative under the direction of their memory address generators to simultaneously access and transfer digital data words to the destination data handling units correspondingly coupled thereto.

Claim 11

The programmed digital memory in accordance with claim 8 including an output data ready logic circuit governed by the signals representative of the states of operation of the plurality of memory address generators and the programmed instructions to generate output permissive signals, each indicating that a selected memory section is ready to access and transfer digital data words to the chosen destination data handling unit correspondingly coupled thereto by the output switching circuit.

Claim 12

The programmed digital memory in accordance with claim 1 including an output switching circuit governed by a select code generated by at least one of a plurality of destination data handling units for selecting an appropriate memory section for said destination data handling unit; and an output data ready logic circuit governed by signals representative of the states of operation of the plurality of memory address generators to generate permissive signals permitting the transfer of data words between said destination data handling unit and its selected memory section.

Claim 13

The programmed digital memory in accordance with claim 1 including an input switching circuit selectively operative to couple one memory section of the plurality to any one of a plurality of source data handling units, and an output switching circuit selectively operative to couple another memory section of the plurality to any one of a plurality of destination data handling units, both operations performed in accordance with the programmed instructions; and wherein said one and another memory sections being operative under the direction of their corresponding memory address generators to store data words from the chosen source data handling unit in said one memory section and access data word for the chosen destination data handling unit from said other memory section, simultaneously.

Claim 14

The programmed digital memory in accordance with claims 7, 10 or 11 including a flag logic circuit for generating flag signals as governed by the programmed instructions and signals representative of the states of operation of the plurality of memory address generators, said flag signals being used logically to further govern the generation of the permissive signals which permit a transfer of data words between selected memory sections and the source and destination data handling units correspondingly coupled thereto.

Claim 15

A programmed digital memory in accordance with claim 13 wherein each memory address generator includes memory address sequencing apparatus for transferring digital data words between its corresponding memory section and a selected one of the source and destination data handling units as conditionally governed by the permissive signals generated by the input and output data ready logic circuits and the flag signals generated by the flag logic circuit.

Claim 16

A digital signal processing system governed by programmed instructions from a source of instructions, said system comprising: at least one signal processor having an input section for accepting digital words for processing and an output section for transferring processed digital words therefrom; at least one source of digital data words for processing by said signal processor; at least one destination unit for accepting processed digital words; and a bulk digital memory operative in response to programmed instructions from said source of instructions to transfer digital data words between itself and said source of digital data words, said destination unit and said signal processor, said bulk digital memory comprising: a plurality of memory sections; a plurality of memory address generators coupled correspondingly to said plurality of memory sections with each memory address generator being operative, simultaneously with and independently of the other memory address generators of said plurality, to control memory address sequencing of its corresponding memory section for the transfer of digital data words, corresponding to said sequenced addresses, between said memory section and a selected one of said source of digital data words, said destination unit, and said signal processor and to generate at least one signal representative of the state of operation thereof; and memory control logic circuitry operative in response to said programmed instructions to distribute each programmed instruction to a correspondingly designated memory address generator in accordance with said signals representative of the states of operation thereof for governing the memory address sequencing operations performed thereby.

Claim 17

A digital signal processing system governed by programmed instructions from a source of instructions, said system comprising: at least one signal processor having an input section for accepting digital words for processing and an output section for transferring processed digital words therefrom; at least one source of digital data words for processing by said signal processor; at least one destination unit for accepting processed digital words; and a bulk digital memory operative in response to programmed instructions from said source of instructions to transfer digital data words between itself and said source of digital data words, said destination unit and said signal processor, said bulk digital memory comprising: a plurality of memory sections; a plurality of memory address generators coupled correspondingly to said plurality of memory sections with each memory address generator being operative, simultaneously with and independently of the other memory address generators of said plurality, to control memory address sequencing of its corresponding memory section for the transfer of digital data words, corresponding to said sequenced addresses, between said memory section and a selected one of said source of digital data words, said destination unit, and said signal processor and to generate at least one signal representative of the state of operation thereof; and memory control logic circuitry operative in response to said programmed instructions to distribute each programmed instruction to a correspondingly designated memory address generator in accordance with said signals representative of the states of operation thereof for governing the memory address sequencing operations performed thereby.

Claim 18

The digital signal processing system in accordance with claim 15 wherein each memory section of said bulk memory comprises a plurality of memory subsections having commonly addressable memory locations for time-multiplexing data word transfer operations; and wherein each memory address generator includes memory address sequencing apparatus for storing selected blocks of digital data words in corresponding blocks of memory locations, comprising a set of commonly addressable memory locations of said memory subsections, in accordance with desired time-multiplexed memory address accessing sequences correspondingly predetermined therefor.

Claim 19

The digital signal processing system in accordance with claim 16 wherein each memory section of said bulk memory comprises an array of memory locations with one addressable index of each of said memory locations being the address of the memory subsection thereof and another addressable index of each of said memory locations being the address of the commonly addressable memory location thereof, said array of memory locations being further subdivided into indexed addressable blocks and subblocks of memory locations to facilitate the time-multiplexed block data word transfer operations, said subblocks comprising the commonly addressable memory locations of the plurality of memory subsections.

Claim 20

The digital signal processing system in accordance with claim 17 wherein the memory address sequencing apparatus of each memory address generator of the bulk memory comprises: a first logic circuit for generating digital timing signals associated with the time-multiplexed memory addressing operations; a second logic circuit for generating digital timing signals associated with the memory address sequence set forth in the programmed instruction distributed thereto; a first counter circuit for generating the address sequence for the memory subsections in connection with the time-multiplexed transfer of the blocks of digital data words as governed by said programmed instruction; a second counter circuit for counting the number of digital data words being transferred in a transfer operation and for generating a signal indicative of the last word transferred in said transfer operation as governed by said programmed instruction; a third counter circuit governed by said programmed instruction for generating the memory address sequence for the memory subblocks in connection with a block transfer operation and for generating a signal indicative of the last subblock transferred in said block transfer operation; a fourth counter circuit governed by said programmed instruction for generating the memory address sequence for the memory blocks in connection with a multiple block transfer operation and for generating a signal indicative of the last block transferred in said multiple block transfer operation; and a third logic circuit for interacting said signals generated by the aforementioned circuits together and with said programmed instruction in accordance with a predetermined logical arrangement to enable and coordinate the operations of said first through fourth counter circuits, said third logic circuit further operative to generate signals indicative of the operational states of the memory address generator.

Claim 21

The digital signal processing system in accordance with claim 15 including an input switching circuit selectively operative to couple any memory section of the plurality to any one of the units selected from the group of digital data word sources and signal processor in accordance with the programmed instructions for collecting and storing digital data words transferred therefrom.

Claim 22

The digital signal processing system in accordance with claim 19 wherein the input switching circuit includes means for selectively coupling more than one memory section correspondingly to more than one unit selected from the group of digital data word sources and signal processors; and wherein said more than one memory sections being operative under the direction of their memory address generators to simultaneously collect and store digital data words from the selected units correspondingly coupled thereto.

Claim 23

The digital signal processing system in accordance with claim 19 including an input data ready logic circuit governed by the signals representative of the states of operation of the plurality of memory address generators and the programmed instructions to generate input permissive signals, each indicating that a selected memory section of the bulk memory is available to collect and store digital words from the selected unit correspondingly coupled thereto by the input switching circuit.

Claim 24

The digital signal processing system in accordance with claim 15 including an output switching circuit selectively operative to couple any memory section of the plurality to any one of the units selected from the group of destination units and signal processor in accordance with the programmed instructions for accessing and transferring digital data words thereto.

Claim 25

The digital signal processing system in accordance with claim 22 wherein the output switching circuit includes means for selectively coupling more than one memory section correspondingly to more than one unit selected from the group of destination units and signal processor; and wherein said more than one memory sections being operative under the direction of their memory address generators to simultaneously access and transfer digital data words to the units correspondingly coupled thereto.

Claim 26

The digital signal processing system in accordance with claim 22 including an output data ready logic circuit governed by the signals representative of the states of operation of the plurality of memory address generators and the programmed instructions to generate output permissive signals, each indicating that a selected memory section is ready to access and transfer digital data words to the selected unit correspondingly coupled thereto by the output switching circuit.

Claim 27

The digital signal processing system in accordance with claim 15 including an output switching circuit governed by a select code generated by at least one unit of the group of destination units and signal processor for selecting an appropriate memory section for said unit; and an output data ready logic circuit governed by signals representative of the states of operation of the plurality of memory address generators to generate permissive signals permitting the transfer of data words between said unit and its selected memory section.

Claim 28

The digital signal processing system in accordance with claim 15 including an input switching circuit selectively operative to couple one memory section of the plurality to any one unit selected from the group of digital data word sources and signal processor, and an output switching circuit selectively operative to couple another memory section of the plurality to any other unit selected from the group of destination units and signal processor, both operations performed in accordance with the programmed instructions; and wherein said one and another memory sections being operative under the direction of their corresponding memory address generators to collect data words from said one selected unit in said one memory section and access data word for said other selected unit from said other memory section, simultaneously.

Claim 29

The digital signal processing system in accordance with claims 21, 24 or 25 including a flag logic circuit for generating flag signals as governed by the programmed instructions and signals representative of the states of operation of the plurality of memory address generators, said flag signals being used logically to further govern the generation of the permissive signals which permit a transfer of data words between selected memory sections and the selected units correspondingly coupled thereto.

Claim 30

A digital signal processing system in accordance with claim 27 wherein each memory address generator includes memory address sequencing apparatus for transferring digital data words between its corresponding memory section and the selected unit coupled thereto as conditionally governed by the permissive signals generated by the input and output data ready logic circuits and the flag signals generated by the flag logic circuit.

Claim 33

The method in accordance with claim 29 wherein the value x i is derived in accordance with the following expression: X.sub.i =N-mn.sub.i, where N=number of data words in block i, m=predetermined number of memory locations in a subblock, and n i =minimum number of subblocks capable of storing the data words of block i.

Claim 34

The method in accordance with claim 29 wherein for values of m from 2 to 8, inclusively, the step of skipping over memory location addresses for a straight addressing sequence of said memory section between successive blocks of data words is conducted in accordance with the following table: ______________________________________ m 0 1 2 3 4 5 6 7 ______________________________________ 2 1 0 3 1 0 0 4 1 0 0 1 5 1 0 0 1 2 6 1 0 0 1 2 3 7 1 0 0 1 2 3 4 8 1 0 0 1 2 3 4 5 ______________________________________ where the numerical contents of the table are representative of the number of memory location addresses of a sequence which are skipped between successive blocks of data words; and wherein for values of m greater than 8, the step of skipping over memory location addresses for a straight addressing sequence of said memory section between successive blocks of data words is conducted in accordance with the following expression: No. of skipped memory location addresses=(m-1)-B, where B is the modulo m value of the number of data words in a block.

Claim 35

The method in accordance with claim 29 wherein the sequencing traversely of the memory locations of the subblocks in one of either a straight (S) or reverse (R) sequential order is conducted in accordance with the following table for values of m from 2 through 8, inclusively: ______________________________________ m 0 1 2 3 4 5 6 7 ______________________________________ 2 S S 3 S S R 4 S S R R 5 S S R R R 6 S S R R R R 7 S S R R R R R 8 S S R R R R R R ______________________________________

Claim 36

The method in accordance with claim 32 wherein for a corner turn sequence in which the addresses of the memory locations of the subblocks are sequentially traversed in a straight order, the step of skipping over memory location addresses between successive blocks of data words is conducted in accordance with the following expression: No. of addresses of sequence skipped=the modulo m value of (m+1-Q), where Q is the modulo m value of the number of data words in a block of the plurality.

Claim 37

The method in accordance with claim 32 wherein for a corner turn sequence in which the addresses of the memory locations of the subblocks are sequentially traversed in a reverse order, the step of skipping over memory location addresses between successive blocks of data words is conducted in accordance with the following expression: No. of addresses of sequence skipped=the modulo m value of (m-1-Q), where Q is the modulo m value of the number of data words in a block of the plurality.